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STM32WL55JC データシート(PDF) 66 Page - STMicroelectronics

部品番号 STM32WL55JC
部品情報  Multiprotocol LPWAN dual core 32-bit Arm® Cortex®-M4/M0 LoRa®, (G)FSK, (G)MSK, BPSK, up to 256KB Flash, 64KB SRAM
PDF  145 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32WL55JC データシート(HTML) 66 Page - STMicroelectronics

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Electrical characteristics
STM32WL55/54xx
66/145
DS13293 Rev 1
PD
Power dissipation at
TA = 85 °C for suffix 6 version
or TA = 105 °C for suffix 7(4)
UFBGA73
-
392.0
mW
TA
Ambient temperature for
suffix 6 version
Maximum power
dissipation
–40
85
°C
Low-power dissipation(5)
105
Ambient temperature for the
suffix 7 version
Maximum power
dissipation
–40
105
Low-power dissipation(5)
125
TJ
Junction temperature range
Suffix 6 version
–40
105
°C
Suffix 7 version
125
1. When the reset is released, the functionality is guaranteed down to VBOR0 min.
2. This formula has to be applied only on the power supplies related to the I/O structure described in Table 19:
STM32WL55/54xx pin definition. Maximum I/O input voltage is the smallest value between min (VDD, VDDA) + 3.6 V and
5.5 V.
3. For operation with voltage higher than min (VDD, VDDA) + 0.3 V, the internal pull-up and pull-down resistors must be
disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 101: Package thermal
characteristics).
5. In low-power dissipation state, TA can be extended to this range, as long as TJ does not exceed TJ max (see Table 101:
Package thermal characteristics).
Table 25. General operating conditions (continued)
Symbol
Parameter
Conditions
Min
Max
Unit



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