 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
STM32WL55JC データシート(PDF) 33 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32WL55JC データシート(HTML) 33 Page - STMicroelectronics |
|
|
33 / 145 page  DS13293 Rev 1 33/145 STM32WL55/54xx Functional overview 48 Relation between MCU and sub-GHz radio operating modes The CPUs and sub-GHz radio have their own operating modes (see the table below). 3.11.1 Reset mode In order to improve the consumption under reset, the I/Os state under and after reset is "analog state" (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal. This excludes the five serial-wire JTAG debug ports that are in pull-up/pull-down after reset. 3.12 Peripheral interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources and, consequently, reducing power-supply consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, LPRun, LPSleep, Stop 0, Stop 1 and Stop 2 modes. Table 9. MCU and sub-GHz radio operating modes CPU operating mode Sub-GHz radio operating mode Description Run, Sleep Sleep, Calibration, Standby, Active (FS, TX, RX)(1) LDO or SMPS regulator active, MCU running in main regulator (MR) mode LPRun, LPSleep Deep-Sleep LDO and SMPS regulator off, MCU running in low power regulator (LPR) mode Sleep, Calibration, Standby, Active (FS, TX, RX) LDO or SMPS regulator active, MCU running in low power regulator (LPR) mode Stop 0 Sleep, Calibration, Standby, Active (FS, TX, RX)(1) LDO or SMPS regulator active, MCU running in main regulator (MR) mode Stop 1 and Stop 2 Deep-Sleep LDO and SMPS regulator off, MCU using low power regulator (LPR) mode Sleep, Calibration, Standby, Active (FS, TX, RX) LDO or SMPS regulator active, MCU using low power regulator (LPR) mode Standby Deep-Sleep LDO and SMPS regulator off, MCU regulator off or on in low power (LPR) mode(2). Sleep, Calibration, Standby, Active (FS, TX, RX) LDO or SMPS regulator active, MCU regulator off or on in low power (LPR) mode(2) Shutdown Deep-Sleep(3) LDO and SMPS regulator off, MCU regulator off 1. In the MCU Run, Sleep and Stop 0 modes, the sub-GHz radio is prevented from entering Deep-sleep mode. 2. When retaining SRAM2 in Standby mode, the MCU uses the low-power regulator (LPR) mode. 3. When the CPU is in Shutdown mode, the sub-GHz radio cannot be activated and is forced in Deep-sleep mode. |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
