STM32WL55JC datasheet(18/145 Pages) STMICROELECTRONICS

18 / 145 page

Functional overview

STM32WL55/54xx

18/145

DS13293 Rev 1

3.6

Security memory management

The devices contain many security blocks both for the sub-GHz MAC layer and the Host

application, such as:

•

securable RNG

•

customer keys storage

•

secure Flash memory partition for CPU2 only access

•

secure SRAM partition, that can be accessed only by CPU2

•

securable sub-GHz radio sub-system

•

securable DMA channels

•

securable AES: 128-and 256-bit AES, supporting ECB, CBC, CTR, GCM, GMAC and

CCM chaining modes

•

securable PKA:

–

modular arithmetic including exponentiation with maximum modulo size of

3136 bits

–

elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA

verification with maximum modulo size of 521 bits

•

cyclic redundancy check calculation unit (CRC)

3.7

Boot modes

At startup, BOOT0 pin and BOOT1 option bit are used to select one of the following boot

options:

•

Boot from user Flash memory

•

Boot from boot system memory (where embedded bootloader is located)

•

Boot from embedded SRAM

•

Boot from system memory (where the embedded SFI is located)

The bootloader makes possible to download code from USART or SPI.

3.8

Global security controller (GTZC)

The GTZC includes the following sub-blocks:

•

TZSC: security controller

This sub-block defines the secure/privileged state of slave peripherals. It also controls

the unprivileged area size for the watermark memory peripheral controller (MPCWM).

•

TZIC: security illegal access controller

This sub-block gathers all illegal access events in the system and generates a secure

interrupt towards the secure CPU2 NVIC.

These sub-blocks are used to configure the system security and privilege such as:

•

on-chip Flash memory and RAM with programmable privileged protection on both

secure and non-secure memory areas

•

AHB and APB peripherals with programmable security and/or privileged access

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