Data Sheet

HMC525ACHIPS

Rev. 0 | Page 5 of 27

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

HMC525ACHIPS

(TOP VIEW)

Not to Scale

GND

RF

GND

3

2

1

GND

LO

GND

7

8

9

4

5

6

NC NC NC

12

11

10

IF1 IF2 GND

NOTES

1. NC = NO CONNECT.

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3, 7, 9, 10

GND

Ground. The GND pads must be connected to RF and dc ground. See Figure 3 for the interface schematic.

2

RF

Radio Frequency Input and Output. The RF pad is dc-coupled and matched to 50 Ω when LO is on. See Figure 4

for the interface schematic.

4, 5, 6

NC

No Connect.

8

LO

Local Oscillator Input. The LO pad is dc-coupled and matched to 50 Ω when LO is on. See Figure 5 for the

interface schematic.

11, 12

IF2, IF1

First and Second Quadrature Intermediate Frequency Input and Output Pads. The IFx pads are dc-coupled. For

applications not requiring operation to dc, use an off-chip dc blocking capacitor. For operations to dc, the IFx

pads must not source or sink more than 3 mA of current. Otherwise, the device may not function and may fail.

See Figure 6 for the interface schematic.

INTERFACE SCHEMATICS

GND

Figure 3. GND Interface Schematic

RF

Figure 4. RF Interface Schematic

LO

Figure 5. LO Interface Schematic

IF1, IF2

Figure 6. IF1, IF2 Interface Schematic