AS4LC2M8S1 datasheet(11/28 Pages) ALSC

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AS4LC2M8S1

AS4LC1M16S1

7/5/00

ALLIANCE SEMICONDUCTOR

Burst read

CS = CAS = A10 = low; RAS =

WE = high; A11 = bank select,

A0~A8 = column address; (A9

= don’t care for 2M × 8; A8,

A9 = don’t care for 1M × 16)

Use the Burst Read command to access a consecutive burst of data from

an active row in an active bank. Burst read can be initiated on any

column address of an active row. The burst length, sequence and

latency are determined by the mode register setting. The first output

data appears after the CAS latency from the read command. The output

goes into a high impedance state at the end of the burst (BL = 1,2,4,8)

unless a new burst read is initiated to form a gapless output data

stream. A full-page burst does not terminate automatically at the end of

the burst. Terminate the burst with a burst stop command, precharge

command to the same bank or another burst read/write

Burst write

CS = CAS = WE = A10 = low;

RAS = high; A0~A9 = column

address; (A9 = don’t care for

2M × 8; A8, A9 = don’t care

for 1M × 16)

Use the Burst Write command to write data into the SDRAM on

consecutive clock cycles to adjacent column addresses. The burst

length and addressing mode is determined by the mode register

opcode. Input the initial write address in the same clock cycle as the

Burst Write command. Burst terminate behavior for write is the same

as that for read.Terminate the burst with a burst stop command,

precharge command to the same bank or another burst read/write.

DQM can also be used to mask the input data.

UDQM/LDQM (×16)

DQM (×8) operation

Use DQM to mask input and output data. It disables the output buffers

in a read operation and masks input data in a write operation. The

output data is invalid 2 clocks after DQM assertion (2 clock latency).

Input data is masked on the same clock as DQM assertion (0 clock

latency).

Burst stop

CS = WE = low; RAS = CAS =

high

Use burst stop to terminate burst operation. This command may be

used to terminate all legal burst lengths.

Bank precharge

CS = A10 = RAS = WE = low;

CAS = high; A11 = bank

select; A0~A9 = don’t care

The Bank Precharge command precharges the bank specified by A11.

The precharged bank is switched from active to idle state and is ready

to be activated again. Assert the precharge command after tRAS(min) of

the bank activate command in the specified bank. The precharge

operation requires a time of tRP(min) to complete.

Precharge all

CS = RAS = WE = low; CAS =

A10 = high; A11, A0~A9 =

don’t care

The Precharge All command precharges both banks simultaneously.

Both banks are switched to the idle state on precharge completion.

Auto precharge

Write: CS = CAS = WE = low ;

Read: CS = CAS = low;

A10 = high; A11 = bank select;

A0~A9 = column address;

(A9 = don’t care for 2M × 8; A8,

A9 = don’t care for 1M × 16)

During auto precharge, the SDRAM adjusts internal timing to satisfy

tRAS(min) and tRP for the programmed CAS latency and burst length.

Couple the auto precharge with a burst read/write operation by

asserting A10 to a high state at the same time the burst read/write

commands are issued. At auto precharge completion, the specified

bank is switched from active to idle state. Note that no new commands

(RD/WR/DEAC) can be issued to the same bank until the specified

bank achieves the idle state. Auto precharge does not work with full-

page burst.

Clock suspend/power

down mode entry

CKE = low

When CKE is low, the internal clock is frozen or suspended from the

next clock cycle and the state of the output and burst address are

frozen. If both banks are idle and CKE goes low, the SDRAM enters

power down mode at the next clock cycle. When in power down

mode, no input commands are acknowledged as long as CKE remains

low. To exit power down mode, raise CKE high before the rising edge

of CLK.

Command

Pin settings

Description

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