FBSGAM02PR50 datasheet(7/33 Pages) EPC-CO

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FBS-GAM02-P-R50 Datasheet

11.) The minimum frequency of operation is determined by the internal bootstrap capacitance and the bias current required by the high-

side power switch gate driver circuit. In order to keep the high-side power switch gate driver bootstrap capacitor properly charged

it is recommended that the maximum duty cycle (ton · fs) of the high-side power switch is limited to the value shown. Accordingly,

the high-side power switch is unsuitable for DC applications with the use of an external DC power supply connected between the

TBST(+) and TOS(-) pins.

12.) For half-bridge applications, a “dead” time delay MUST be added between the time when the BOUT output transitions ON-TO-OFF

and the TOUT output transitions OFF-to-ON, and also when the TOUT output transitions ON-to-OFF and the BOUT output transitions

OFF-to-ON, to avoid both power switches being actuated simultaneously. Simultaneous actuation of the high-side and low-side

power switches causes very large, uncontrolled and destructive currents to flow through the ON-state switches from VDD to PGND.

In order to calculate the desired output dead times (tDEAD), the delay time from BIN transitioning from logic 1-to-0 to TIN transitioning

from logic 0-to-1 is:

td1 = (tLSd(OFF) + tLSf ) + tDEAD – (tHSd(ON) + tHSr ),

where the LS nomenclature refers to the low-side driver off-delay and fall times and the HS nomenclature refers to the high-side

driver on-delay time and rise time.

The delay time from TIN transitioning from logic 1-to-0 to BIN transitioning from logic 0-to-1 is:

td2 = (tHSd(OFF) + tHSf ) + tDEAD – (tLSd(ON) + tLSr ),

where the HS nomenclature refers to the high-side driver off-delay and fall times and the LS nomenclature refers to the low-side

driver on-delay time and rise time.

13.) The maximum dead time prevents the Schottky clamp diodes in the power switch outputs from being overstressed and damaged

by excessive power dissipation. The maximum dead time is limited by the switching frequency and by the power dissipation of the

Schottky diodes: Pd = Vf · Io · 2 · td/T. Please refer to Figures 27, 28, and 30.

14.) The input shoot-through protection is activated if both the BIN and TIN logic inputs are set to the logic high (“1”) condition

simultaneously. In the case where the BIN and TIN inputs are set to logic high, both the low- and high-side power switches are set to

their high impedance (OFF) state.

15.) VDD = 50 VDC, ID = +/-10 A and fs = 1.0 MHz. Half-bridge configuration.

16.) The maximum switching frequency is limited by power dissipation in the half-bridge configuration, and not by throughput delay

times. Faster switching frequencies are possible at reduced VDD and Io operating levels and at reduced ambient operating

temperatures. See Figures 23 through 26.

17.) See Figure 22.

18.) Half-bridge configuration. Current from pin 12 to pin 11 (high-side Schottky) or pin 14 to pin 13 (low-side Schottky), not drawn

simultaneously. Pulse duration = 500 μs. Repetition rate = 5 seconds.

19.) Half-bridge configuration. Current from pin 11 to pin 12 or pin 12 to pin 11 (High-side Power Switch), or pin 13 to pin 14 or pin 14 to

pin 13 (low-side Power Switch), not drawn simultaneously. Pulse duration = 500 μs. Repetition rate = 5 seconds.

Specification Notes (continued)

BIN

TIN

td1

td2

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