ECE1200 datasheet(36/87 Pages) MICROCHIP

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ECE1200

DS00003093C Draft-page 36

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6.7

System Settings

The following items constitute a list of Chipset options to be addressed in the design process.

6.7.1

SET UP SOFT-STRAPS FOR ESPI

The ECE1200 device is capable of operating at the 50MHz eSPI DC and AC specifications. However, it does not itself

enforce this limit. The Chipset’s PCH Soft-Strap settings (in Flash) must select this, or a lower frequency, as the maxi-

mum for correct operation.

Other Soft-Strap selections will choose such eSPI options as the bus width and the number of Slave devices. These

selections are communicated to the Slave(s) by Chipset hardware actions, and do not involve any software setup.

6.7.2

DEFER PCH SUSWARN# AND SUSACK# PINS TO ECE1200

The earliest eSPI-capable PCH devices have lost the SUSWARN# and SUSACK# pins in the trade-off to support eSPI,

requiring that these pins be implemented as Virtual Wires instead. For this reason, these pins are re-created on the

ECE1200 pinout. SUSWARN# and SUSACK# represent a mandatory handshake in any system that uses the Intel Deep

Sleep Well (DSW) state. SUSWARN# is an output pin, and the SUSACK# input pin must follow it, both rising and falling

edges, with an optional system-imposed external delay if necessary. It is acceptable to tie these pins together in the

simplest case.

In later PCH devices, these pins may again be provided on the PCH itself. In at least one case (IceLake), these pins are

provided, but multiplexed with the SMBus “SMLink1” pins, with SUSWARN# / SUSACK# being the default. If the

SMLink1 capability is needed (for Chipset Temperature and RTC Register access) then it must be selected, and the

SUSWARN# / SUSACK# functionality can still come from the ECE1200 device as Virtual Wires instead. For pre-boot

configuration of the PCH pins, see the Intel documentation.

If, however, it is desired to keep the SUSWARN# / SUSACK# pin functionality on the PCH pins, then it is recommended

that the SUSACK# pin on the ECE1200 device be tied permanently low (its expected default state) so that Virtual Wire

traffic from it does not get transmitted to the Chipset.

If the ECE1200 device is connected to eSPI Chip Select #1 (with the BOOT_DONE pin held low), then it does not par-

ticipate in the SUSWARN# / SUSACK# handshakes, though it will still present the SUSWARN# state on its own output

pin. This handshake, and considerations for providing it, become instead a system design decision between the “Pri-

mary” eSPI device on Chip Select #0 and the PCH.

6.8

Initialization Steps

Listed below are the recommendations for establishing communication with the ECE1200 and performing setup.

6.8.1

LPC SETUP (NONE)

There is no setup of the ECE1200 required to begin LPC traffic. The LPC bus receives all I/O and Memory traffic that is

routed to the ECE1200 by the Chipset, except for two bytes at its I/O Base Address for internal register access.

6.8.2

BASE ADDRESS RE-ASSIGNMENT (OPTIONAL)

From its reset state, the ECE1200 device’s access portal for internal registers is configured to occupy I/O addresses

008Ch and 008Dh in order to avoid addressing conflict with other legacy devices. In nearly all system configurations, it

is accessible immediately at these addresses, requiring no special routing considerations within the Host Chipset. But

the ECE1200 may also be re-configured, if desired, in order to move it into another I/O region.

The default addresses reside in an unused section of the Host Chipset’s Port 80h region (also called the “Debug Port

region” or “RPR region”) of the Host I/O space, where 8Ch is the INDEX location and 8Dh is the DATA location. The I/O

address of the INDEX location is called the ECE1200 device’s “Base Address”.

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