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STE2007 データシート(PDF) 25 Page - STMicroelectronics |
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STE2007 データシート(HTML) 25 Page - STMicroelectronics |
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25 / 62 page ![]() STE2007 4 INTERFACE 25/62 4.3.4 Driver TxData Mode (Read Mode) If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit during the last write access, is set to a logic 0, the byte read is the status byte. Figure 17. Communication Protocol LR0008d MASTER ACK COMMUNICATION START I2C START COND 0 11 1 1 0 A STE2007 ACK R/W SLAVE ADDRESS SA1 Co A Control Byte COMMAND Byte A STE2007 ACK STE2007 ACK Command Byte D/C 000 10 SINGLE COMMAND SEQUENCE Co A Control Byte COMMAND Byte A STE2007 ACK STE2007 ACK First Command Byte D/C 000 00 MULTIPLE COMMAND SEQUENCE COMMAND Byte A STE2007 ACK Last Command Byte Co A Control Byte STE2007 ACK D/C 000 11 SINGLE DATA SEQUENCE MULTIPLE DATA SEQUENCE DATA Byte A Data Byte STE2007 ACK Co A Control Byte DATA Byte A STE2007 ACK STE2007 ACK First Data Byte D/C 000 01 DATA Byte A STE2007 ACK Last Data Byte COMMUNICATION STOP I2C STOP COND STATUS BYTE READ SEQUENCE I2C START COND 01111 0 A STE2007 ACK R/W SLAVE ADDRESS A I2C START COND STATUS Byte READ MODE WRITE MODE SA2 000 000 000 000 SA1 SA2 |
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