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Z8F082ASH020SC データシート(PDF) 66 Page - Zilog, Inc.

部品番号 Z8F082ASH020SC
部品情報  Z8 Encore XP-R F08xA Series with eXtended Peripherals
PDF  244 Pages
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メーカー  ZILOG [Zilog, Inc.]
ホームページ  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8F082ASH020SC データシート(HTML) 66 Page - Zilog, Inc.

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PS024705-0405
P R E L I M I N A R Y
Interrupt Controller
Z8 Encore! XP® F08xA Series
Product Specification
48
Architecture
Figure 7 illustrates the interrupt controller block diagram.
Figure 7.Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
• Execution of an EI (Enable Interrupt) instruction
• Execution of an IRET (Return from Interrupt) instruction
Lowest
0036H
Port C0, both input edges
0038H
Reserved
Table 31. Trap and Interrupt Vectors in Order of Priority (Continued)
Priority
Program Memory
Vector Address
Interrupt or Trap Source
Vector
IRQ Request
High
Priority
Medium
Priority
Low
Priority
Priority
Mux
Port Interrupts
Internal Interrupts



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