Z8F082ASH020SC datasheet(85/244 Pages) ZILOG

85 / 244 page

PS024705-0405

P R E L I M I N A R Y

Timers

Z8 Encore! XP® F08xA Series

Product Specification

1. Write to the Timer Control register to:

–

Disable the timer

–

Configure the timer for CAPTURE mode.

–

Set the prescale value.

–

Set the Capture edge (rising or falling) for the Timer Input.

2. Write to the Timer High and Low Byte registers to set the starting count value

(typically 0001H).

3. Write to the Timer Reload High and Low Byte registers to set the Reload value.

4. Clear the Timer PWM High and Low Byte registers to 0000H. Clearing these

registers allows user software to determine if interrupts were generated by either a

capture event or a reload. If the PWM High and Low Byte registers still contain

0000H

after the interrupt, the interrupt was generated by a Reload.

5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing

to the relevant interrupt registers. By default, the timer interrupt is generated for both

input capture and reload events. If appropriate, configure the timer interrupt to be

generated only at the input capture event or the reload event by setting TICONFIG

field of the TxCTL1 register.

6. Configure the associated GPIO port pin for the Timer Input alternate function.

7. Write to the Timer Control register to enable the timer and initiate counting.

In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated

using the following equation:

CAPTURE RESTART Mode

In CAPTURE RESTART mode, the current timer count value is recorded when the accept-

able external Timer Input transition occurs. The Capture count value is written to the

Timer PWM High and Low Byte Registers. The timer input is the system clock. The

TPOL

bit in the Timer Control register determines if the Capture occurs on a rising edge or

a falling edge of the Timer Input signal. When the Capture event occurs, an interrupt is

generated and the count value in the Timer High and Low Byte registers is reset to 0001H

and counting resumes. The INPCAP bit in TxCTL1 register is set to indicate the timer

interrupt is because of an input capture event.

If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the

Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer

generates an interrupt, the count value in the Timer High and Low Byte registers is reset to

0001H

and counting resumes. The INPCAP bit in TxCTL1 register is cleared to indicate

the timer interrupt is not caused by an input capture event.

Capture Elapsed Time (s)

Capture Value

Start Value

–

() Prescale

System Clock Frequency (Hz)

----------------------------------------------------------------------------------------------------

Z8F082ASH020SC データシート(PDF) 85 Page - Zilog, Inc.

Z8F082ASH020SC データシート(HTML) 85 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード