8.3.2.5 Latch-Up Immunity

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The Latch-up condition typically requires a power cycle to eliminate the

low impedance path.

An insulating oxide layer is placed on top of the silicon substrate to prevent any parasitic junctions from forming

in the TMUX7462F devices. As a result, the devices are latch-up immune under all circumstances by device

construction.

8.3.2.6 EMC Protection

The TMUX7462F is not intended for standalone electromagnetic compatibility (EMC) protection in industrial

applications. There are three common high voltage transient specifications that govern industrial high voltage

transient specifications: IEC61000-4-2 (ESD), IEC61000-4-4 (EFT), and IEC61000-4-5 (surge immunity). A

transient voltage suppressor (TVS), along with some low-value series current limiting resistor, are required to

prevent source input voltages from going above the rated ±60 V limits.

It is critical to ensure that the maximum working voltage is greater than the normal operating range of the input

source pins protected and any known system common-mode overvoltage that may be present due to incorrect

wiring, loss of power, or short circuit when selecting a TVS protection device. Figure 8-2 shows an example of

the proper design window when selecting a TVS device.

Region 1 denotes the normal operation region of TMUX7462F, where the input source voltages stay below

overvoltage fault) presented on the source input pins. Region 3 represents the margin between any known

DC overvoltage level and the absolute maximum rating of the TMUX7462F. The TVS breakdown voltage must

be selected to be less than the absolute maximum rating of the TMUX7462F, but greater than any known

possible persistent DC or long duration AC overvoltage fault to avoid triggering the TVS inadvertently. Region 4

represents the margin the system designers must impose when selecting the TVS protection device to prevent

accidental triggering the ESD cells of the TMUX7462F.

Normal Operation

Fault Voltage

System

Overvoltage

Overvoltage

Protection Window

Device Absolute

Max Rating

Internal ESD

Trigger Voltage

1

2

3

4

TVS

Breakdown

Voltage

Fault Voltage

0 V

Overvoltage

Protection Window

2

3

4

TVS

Breakdown

Voltage

System

Overvoltage

Device Absolute

Max Rating

Internal ESD

Trigger Voltage

Figure 8-2. System Operation Regions and Proper Region of Selecting a TVS Protection Device

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TMUX7462F

SCDS394A – MARCH 2021 – REVISED OCTOBER 2021

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