LTM4650 datasheet(77/138 Pages) AD

77 / 138 page

LTM4664A

Rev. 0

For more information www.analog.com

Configuration section replicates or conveys normal oper-

ating conditions of a µModule regulator. For example, in

normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through the

bottom of the µModule package—as the standard defines

for θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4664A, be aware there are multiple

power devices and components dissipating power, with

a consequence that the thermal resistances relative to

different junctions of components or die are not exactly

linear with respect to total package power loss. To rec-

oncile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the LTM4664A and the specified PCB with

all of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-9 and JESD51-12 to predict power loss heat

flow and temperature readings at different interfaces

that enable the calculation of the JEDEC-defined thermal

resistance values; (3) the model and FEA software is used

to evaluate the LTM4664A with heat sink and airflow; (4)

having solved for and analyzed these thermal resistance

values and simulated various operating conditions in the

software model, a thorough laboratory evaluation repli-

cates the simulated conditions with thermocouples within

a controlled environment chamber while operating the

device at the same power loss as that which was sim-

ulated. The outcome of this process and due diligence

yields the set of derating curves provided in later sections

of this data sheet, along with well-correlated JESD51-12-

defined θ values provided in the Pin Configuration section

of this data sheet.

The 1.0V and 1.5V power loss curves in Figure 39 and

40 respectively can be used in coordination with the load

current derating curves in Figure 41 to 44 for calculating

an approximate θJA thermal resistance for the LTM4664A

with various heat sinking and airflow conditions. These

thermal resistances represent demonstrated performance

of the LTM4664A on hardware; a 8-layer FR4 PCB mea-

suring 99mm × 145mm × 1.6mm using 2oz copper on

all layers. The power loss curves are taken at room tem-

perature, and are increased with multiplicative factors of

1.35 when the junction temperature reaches 125°C. The

derating curves are plotted with the LTM4664A’s paral-

leled outputs initially sourcing up to 50A and the ambient

temperature at 50°C. The output voltages are 1.0V and

1.5V. These are chosen to include the lower and higher

output voltage ranges for correlating the thermal resis-

tance. Thermal models are derived from several tempera-

ture measurements in a controlled temperature chamber

along with thermal modeling analysis. The junction tem-

peratures are monitored while ambient temperature is

increased with and without airflow.

The power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at 125°C maximum while lowering output cur-

rent or power while increasing ambient temperature. The

decreased output current decreases the internal module

loss as ambient temperature is increased. The monitored

junction temperature of 120°C minus the ambient operat-

ing temperature specifies how much module temperature

rise can be allowed. As an example in Figure 41, the load

current is derated to ~30A at ~97°C ambient with no air

or heat sink and the room temperature (25°C) power loss

for this 48VIN to 1.0VOUT at 30AOUT condition is ~3.2W. A

4.32W loss is calculated by multiplying the ~3.2W room

temperature loss from the 48VIN to 1.0VOUT power loss

curve at 30A (Figure 41), with the 1.35 multiplying fac-

tor. If the 97°C ambient temperature is subtracted from

the 120°C junction temperature, then the difference of

23°C divided by 4.32W yields a thermal resistance, θJA,

of 5.3°C/W—in good agreement with Table 11. Table 10

and 11 provide equivalent thermal resistances for 1.0V

and 1.5V outputs with and without airflow. The derived

DUAL 25A/30A PSM APPLICATIONS INFORMATION

LTM4650 データシート(PDF) 77 Page - Analog Devices

LTM4650 データシート(HTML) 77 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード