LTM4650 datasheet(21/138 Pages) AD

21 / 138 page

LTM4664A

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

INTVCCS2: (G7) Output of the 5.5V internal linear low

dropout regulator. The driver and control circuits are

powered from this voltage source. Must be bypassed to

power ground with a minimum of 4.7μF ceramic or other

low ESR capacitor. Do not use the INTVCCS2 pin for any

other ICs.

VOUT2: (H1-H3) 2nd stage divide by two output pins.

These pins connect to the VINS3 input of dual 25A/30A

PMBus converter. Recommend placing output decoupling

capacitance directly between these pins and GND pins.

PGOODS2: (H5) This is an Open Drain Output Pin.

PGOODS2 is pulled to ground if there are any faults or

the voltage at UVS2 pin is lower than 1V. Use PGOOD2 or

FAULTS2 to sequence on RUN_C0, and RUN_C1 for the

dual 25A/30A stage.

FAULTS2: (H6) This is an Open Drain Output Pin. FAULTS2

is pulled to ground when the VOUT2 voltage is out of

the (VINS2)/2 window threshold or the voltage between

INSNSS2+ and INSNSS2– is higher than 50mV. FAULTS2

pin is released after INTVCCS2 starts up and passes UVLO.

Use FAULTS2 or PGOOD2 to sequence on RUN_C0, and

RUN_C1 for the dual 25A/30A PSM stage.

UVS2: (H7) Undervoltage Comparator. If the UVS2 pin

voltage is lower than 1V, the PGOODS2 pin is pulled

down. If the UV pin voltage is higher than 1V and no faults,

PGOODS2 pin is released. Connect to INTVCCS2 if not

used. This pin is used to validate proper output regulation.

PMBus Dual 25A/30A Section

VOUTC1 (A1-A7, B4-B7): Channel 1 Output Voltage. Place

recommended output capacitors from this connection to

GND. See recommended layout in Figure 45.

VOUTC0: (A10-A16, B10-B13): Channel 0 Output Voltage.

Place recommended output capacitors from this connec-

tion to GND. See recommended layout in Figure 45.

FSWPH_CFG (H8): Switching Frequency, Channel

Phase Interleaving Angle and Phase Relationship to

SYNC Configuration Pin. If this pin is left open—or, if

the dual 25A/30A regulator is configured to ignore pin-

strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6]

= 1b—then the LTM4664A’s switching frequency

(FREQUENCY_SWITCH) and channel phase relation-

ships (with respect to the SYNC clock; MFR_PWM_

CONFIG[2:0]) are dictated at SVIN power-up according

to the LTM4664A’s NVM contents. Default factory values

are: 350kHz operation; Channel 0 at 0°; and Channel 1 at

180°C (convention throughout this document: a phase

angle of 0° means the channel’s switch node rises coinci-

dent with the falling edge of the SYNC pulse). Connecting

a resistor divider from VDD25 to SGND_C0_C1, see page

4 (and using the factory default NVM setting of MFR_

CONFIG_ALL[6] = 0b) allows a convenient way to con-

figure multiple LTM4664As with identical NVM contents

for different switching frequencies of operation and phase

interleaving angle settings of intra- and extra-module-par-

alleled channels—all, without GUI intervention or the

need to “custom preprogram” module NVM contents.

(See the Dual 25A/30A PSM Applications Information

section.) Minimize capacitance—especially when the pin

is left open—to assure accurate detection of the pin state.

VTRIMC1_ CFG (J5): Output Voltage Select Pin for VOUTC1,

Fine Setting. Works in combination with VOUTC1_CFG

to affect the VOUT_COMMAND (and associated output

voltage monitoring and protection/fault-detection thresh-

olds) of Channel 1, at SVIN power-up. (See VOUTC1_CFG

and the Dual 25A/30A PSM Applications Information sec-

tion.) Minimize capacitance—especially when the pin is

left open—to assure accurate detection of the pin state.

Note that use of RCONFIGs on VOUTC1_CFG/VTRIMC1_

CFG can affect the VOUTC1 range setting (MFR_PWM_

MODE1 [1]) and loop gain. A resistor divider from VDD25

to SGND_C0_C1 can set the trim value, see page 43.

VOUTC0_CFG (J6): Output Voltage Select Pin for VOUTC0,

Coarse Setting. If the VOUTC0_CFG and VTRIMC0_CFG

pins are both left open—or, if the LTM4664A is con-

figured to ignore pin-strap (RCONFIG) resistors, i.e.,

MFR_CONFIG_ALL[6] = 1b—then the LTM4664A's tar-

get VOUTC0 output voltage setting (VOUT_COMMAND0)

and associated power good and OV/UV warning and fault

thresholds are dictated at SVIN power-up according to

the LTM4664A’s NVM contents. A resistor connected

from this pin to SGND—in combination with resistor pin

settings on VTRIMC0_CFG, and using the factory-default

NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used

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