ADA4254ARUZ-R7 datasheet(54/59 Pages) AD

部品番号	ADA4254ARUZ-R7

部品情報	Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier

PDF	59 Pages

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メーカー	AD [Analog Devices]

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54 / 59 page

ADA4254

Data Sheet

Rev. B | Page 54 of 59

ERROR CONFIGURATION REGISTER

Table 27. CFG_C Register Details (Register 0x0D)

Bit Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ERR_LATCH_DIS

Reserved

ERR_DELAY[3:0]

Access

Reserved

Reset

Reserved

Bit 7, ERR_LATCH_DIS—Disable Error Latching

By default, ERR_LATCH_DIS is cleared to 0 and error flags are

latched and require resetting. Setting ERR_LATCH_DIS to 1

makes the errors appear transparently (nonlatching) on the

respective outputs. When ERR_LATCH_DIS is set to 1, errors

can be suppressed for the time interval configured by

ERR_DELAY.

Bits[3:0], ERR_DELAY[3:0] —Error Suppression Time

When ERR_LATCH_DIS is set to 1, ERR_DELAY determines

the number of clock cycles an error must remain present before

the error flag is tripped, which eliminates false trips due to

noise and transients.

Table 28. Error Flag Suppression Time

ERR_DELAY[3:0]

Clock Cycles (μS)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

127

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