L9945TR datasheet(44/151 Pages) STMICROELECTRONICS

44 / 151 page

Figure 22. SPI timing diagram

GADG2802171207PS

NCS

SCK

SDI

SDO

thclcl_app

Tsclk

tscld

tcsdv

tpcld

thcld

tcll

tclh

tsclcl

tpchdz

tON_NCS

Figure 22 shows that the device has CPOL = 0 and CPHA = 1. During Reset, SDO is forced into a high

impedance state and any inputs from SCLK and SDI are ignored.

5.9.5

SPI protocol

The SPI protocol features frames structured as follows:

Table 29. SPI protocol

Command

Data

MSB

LSB

MOSI

R/W

D26

D25

D24

D23

D22

D21

D20

….

MISO

R/W

R26

R25

R24

R23

R22

R21

R20

….

The MSB of each frame will be shifted in/out first. Each frame is equipped with an odd parity bit (LSB).

The response is out of frame, so the response to Nth frame will be received when sending the (N+1)th frame.

Figure 23. Out of frame response

GADG2802171255PS

SDI

frame A

(previous

response)

response to

frame A

response to

frame B

frame C

SDO

The response frame 0x00000000 will be issued in the following cases:

•

After a reset event (POR or NRES assertion)

•

Invalid command received (see Table 30. SPI MOSI list for the list of available commands)

•

Number of SCK pulses not multiple of 32

•

Parity error on the received command

Chip select (NCS) assertion without any following SCK pulse is ignored and doesn't generate any error. In order

to ignore spurious transitions, NCS input is equipped with a deglitch filter tfNCS.

L9945

Serial Peripheral Interface (SPI)

DS12275 - Rev 8

page 44/151

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