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LT8686SJVPBF データシート(PDF) 14 Page - Analog Devices

部品番号 LT8686SJVPBF
部品情報  42V Quad, Gangable, Synchronous, Monolithic Step-Down Regulator
PDF  26 Pages
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LT8686SJVPBF データシート(HTML) 14 Page - Analog Devices

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LT8686S
14
Rev. 0
For more information www.analog.com
3MHz. See the Applications Information section for fur-
ther frequency selection information.
The oscillator generates four-clock phases. When operat-
ing independently, the relative phases of the channels are
0° for CH1, 180° for CH2, 270° for CH3 and 90° for CH4.
Multiphase operation reduces input current ripple ampli-
tude while increasing the ripple frequency resulting in
lower required input capacitance. When combining chan-
nels, the master channel phase determines the combined
channel’s clock phase.
MODE SELECTION AND SYNCHRONIZATION
The LT8686S offers two primary operating modes, Burst
Mode operation and pulse-skipping mode, plus the
option to select frequency spread-spectrum for each. In
pulse-skipping mode, all switching cycles remain aligned
to the internal clock. Further, full switching frequency is
maintained to lower load currents than Burst Mode oper-
ation. Conversely, Burst Mode operation reduces input
current at low load currents, thereby achieving higher
low load efficiency than pulse-skipping mode. Selecting
spread-spectrum results in frequency modulation of
the programmed clock frequency to reduce EMI/EMC
emissions. When selected, the clock frequency will vary
between the programmed frequency and the programmed
frequency plus approximately 20%.
The SYNC/MODE pin is used to select the desired oper-
ating mode. To select low ripple, high efficiency Burst
Mode operation, connect the SYNC/Mode pin to ground.
Alternatively, connect a 26k (5% tolerance or better)
resistor to enable low ripple high efficiency Burst Mode
operation with spread spectrum. To select pulse-skipping
mode, float the SYNC/MODE pin, or to enable pulse skip-
ping with spread spectrum connect the SYNC/MODE pin
to INTVCC.
Finally, the LT8686S may be synchronized to an external
clock source by driving the SYNC/MODE pin with a clock
signal that has a minimum high voltage of 1.5V and max-
imum low voltage of 0.4V. The minimum required pulse
width is 100ns for a high pulse and 100ns for a low pulse.
When syncing, the RT resistor should be chosen to set the
LT8686S switching frequency close to the synchroniza-
tion frequency. The LT8686S will operate in pulse-skip-
ping mode while synchronized to an external clock.
INTVCC REGULATOR
The INTVCC regulator supplies internal LT8686S circuitry.
The current draw will depend on the operating frequency,
the higher the switching frequency, the greater the current
drawn from INTVCC. The regulator is supplied by VIN1 at
start-up, but it will draw its supply current from bias if
the bias voltage is above 4.5V and VVIN1 is greater than
VBIAS + 1V. If the BIAS pin is connected to a switching
regulator channel ≥ 4.5V it will improve efficiency, reduce
on-chip power dissipation, and lower the required cur-
rent. The INTVCC regulator may be used to configure other
input pins and output pull-ups related to the LT8686S. It
should not be used to connect to any components not
related to the LT8686S to avoid unexpected interactions.
OPERATION



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