NRF9160-SICA-R7 datasheet(90/400 Pages) NORDIC

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Peripherals

One-to-one connection

This example shows how to create a one-to-one connection between TIMER compare register and SAADC

start task.

The channel configuration is set up first. TIMER0 will publish its COMPARE0 event on channel 0, and

SAADC will subscribe its START task to events on the same channel. After that, the channel is enabled

through the DPPIC.

NRF_TIMER0->PUBLISH_COMPARE0 = (DPPI_PUB_CHIDX_Ch0) |

(DPPI_PUB_EN_Msk);

NRF_SAADC->SUBSCRIBE_START

= (DPPI_SUB_CHIDX_Ch0) |

(DPPI_SUB_EN_Msk);

NRF_DPPIC->CHENSET = (DPPI_CHENSET_CH0_Set << DPPI_CHENSET_CH0_Pos);

Many-to-many connection

The example shows how to create a many-to-many connection, showcasing the DPPIC's channel group

functionality.

A channel group that includes only channel 0 is set up first. Then the GPIOTE and TIMER0 configure their

IN0 and COMPARE0 events respectively to be published on channel 0, while the SAADC configures its

START task to subscribe to events on channel 0. Through DPPIC, the CHG0 DISABLE task is configured

to subscribe to events on channel 0. After an event is received on channel 0 it will be disabled. Finally,

channel 0 is enabled using the DPPIC task to enable a channel group.

NRF_DPPIC->CHG[0] = (DPPI_CHG_CH0_Included << PPI_CHG_CH0_Pos);

NRF_GPIOTE->PUBLISH_IN0

= (DPPI_PUB_CHIDX_Ch0) |

(DPPI_PUB_EN_Msk);

NRF_TIMER0->PUBLISH_COMPARE0

= (DPPI_PUB_CHIDX_Ch0) |

(DPPI_PUB_EN_Msk);

NRF_SAADC->SUBSCRIBE_START

= (DPPI_SUB_CHIDX_Ch0) |

(DPPI_SUB_EN_Msk);

NRF_DPPIC->SUBSCRIBE_CHG[0].DIS = (DPPI_SUB_CHIDX_Ch0) |

(DPPI_SUB_EN_Msk);

NRF_DPPIC->TASK_CHG[0].EN = 1;

6.2.4 Special considerations for a system implementing TrustZone for

Cortex-M processors

DPPI is implemented with split security, meaning it handles both secure and non-secure accesses. In a

system implementing the TrustZone for Cortex-M technology, DPPI channels can be defined as secure or

non-secure using the SPU.

A peripheral configured as non-secure will only be able to subscribe to or publish on non-secure DPPI

channels. A peripheral configured as secure will be able to access all DPPI channels. DPPI handles both

secure and non-secure accesses, but behaves differently depending on the access type:

• A non-secure peripheral access can only configure and control the DPPI channels defined as non-secure

in the SPU.DPPI.PERM[] register(s)

4418_1315 v2.0

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