6.1.4

Watchdog

The IC is composed by two chips (Logic Stage and Process Stage) supplied by two independent and galvanic

isolated sources (VDD/GNDDD and VCC/GNDCC pins, respectively). The IC provides a watchdog function in order

to guarantee a safe condition for the Process Stage when VDD (or GNDDD) supply voltage is missing. If the Logic

Stage does not update the output status within tWD, all the outputs of the Process Stage are disabled until a new

update request is received. The Logic Stage chip periodically sends a refresh signal to the Process Stage chip.

The refresh signal is also considered a valid update signal to reset the timeout counter on the Process Stage, so

the isolated side watchdog does not protect the system from a failure of the host controller (e.g., MCU freezing).

Figure 7. Watchdog behavior

6.1.5

Output enable (OUT_EN)

This pin provides a fast way to disable all the outputs simultaneously. When the OUT_EN pin is driven low for at

least tW(OUT_EN), all eight outputs are disabled. This timing execution is compatible with an external reset push

from the operator, safety requirements, and permits, in a PLC system, a micro-controller polling for obtain all

internal information during a reset procedure.

Figure 8. OUT_EN without effect on output

Figure 9. OUT_EN effective on output channel

ISO808, ISO808-1

Parallel interface

DS14169 - Rev 1

page 16/38