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ST72334J2T3 データシート(PDF) 37 Page - STMicroelectronics |
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ST72334J2T3 データシート(HTML) 37 Page - STMicroelectronics |
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37 / 125 page  ST72334J/N, ST72314J/N, ST72124J 37/125 INTERRUPTS (Cont’d) Figure 26. Interrupt Processing Flowchart Table 6. Interrupt Mapping N ° Source Block Description Register Label Priority Order Exit from HALT Address Vector RESET Reset N/A Highest Priority Lowest Priority yes FFFE h-FFFFh TRAP Software Interrupt no FFFCh-FFFDh 0 Not used FFFA h-FFFBh 1 MCC CSS Main Clock Controller Time Base Interrupt or Clock Security System Interrupt MCCSR CRSR yes FFF8h-FFF9h 2 EI0 External Interrupt Port A3..0 N/A FFF6h-FFF7h 3 EI1 External Interrupt Port F2..0 FFF4h-FFF5h 4 EI2 External Interrupt Port B3..0 FFF2h-FFF3h 5 EI3 External Interrupt Port B7..4 FFF0h-FFF1h 6 Not used FFEEh-FFE Fh 7 SPI SPI Peripheral Interrupts SPISR no FFECh-FFE Dh 8 TIMER A TIMER A Peripheral Interrupts TASR FFEAh-FFEBh 9 TIMER B TIMER B Peripheral Interrupts TBSR FFE8h-FFE 9h 10 SCI SCI Peripheral Interrupts SCISR FFE6h-FFE 7h 11 Data-EEPROM Data EEPROM Interrupt EECSR FFE4h-FFE 5h 12 Not used FFE2h-FFE 3h 13 FFE0h-FFE 1h BIT I SET Y N IRET Y N FROM RESET LOAD PC FROM INTERRUPT VECTO R STACK PC, X, A, CC SET I BIT FETCH NEXT INSTR UCTION EXECU TE INSTRUCTION THIS CLEARS I BIT BY DEFAULT RESTORE PC, X, A, CC FROM STACK BIT I SET Y N |
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