ST72334J2T3 datasheet(49/125 Pages) STMICROELECTRONICS

部品番号	ST72334J2T3

部品情報	8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

PDF	125 Pages

Scroll/Zoom	100%

メーカー	STMICROELECTRONICS [STMicroelectronics]

ホームページ	http://www.st.com

Logo

49 / 125 page

ST72334J/N, ST72314J/N, ST72124J

49/125

MISCELLANEOUS REGISTERS (Cont’d)

MISCELLANEOUS REGISTER 2 (MISCR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = Reserved

Must always be cleared

Bit 5:4 = BC[1:0]

Beep control

These 2 bits select the PF1 pin beep capability.

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the

consumption.

Bit 3:2 = Reserved

Must always be cleared

Bit 1 = SSM

SS mode selection

It is set and cleared by software.

0: Normal mode - SS uses information coming

from the SS pin of the SPI.

1: I/O mode, the SPI uses the information stored

into bit SSI.

Bit 0 = SSI

SS internal mode

This bit replaces pin SS of the SPI when bit SSM is

set to 1. (see SPI description). It is set and cleared

by software.

Table 11. Miscellaneous Register Map and Reset Values

BC1

BC0

SSM

SSI

BC1 BC0

Beep mode with fOSC=16MHz

Off

~2-KHz

Output

Beep signal

~50% duty cycle

~1-KHz

~500-Hz

Address

(Hex.)

Label

765

321

0020h

MISCR1

Reset Value

IS11

IS10

MCO

IS21

IS20

CP1

CP0

SMS

0040h

MISCR2

Reset Value

BC1

BC0

SSM

SSI

ST72334J2T3 データシート(PDF) 49 Page - STMicroelectronics

ST72334J2T3 データシート(HTML) 49 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード