HC705P6AGRSSLASHD datasheet(74/134 Pages) NXP

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Capture/Compare Timer

General Release Specification

MC68HC705P6A — Rev. 1.0

Capture/Compare Timer

8.4.6 Output Compare Registers (OCRH and OCRL)

When the value of the 16-bit counter matches the value in the output

compare registers, the planned TCMP pin action takes place. Writing to

OCRH before writing to OCRL inhibits timer compares until OCRL is

written. Reading or writing to OCRL after the timer status register clears

the output compare flag (OCF).

Figure 8-7. Output Compare Registers (OCRH and OCRL)

To prevent OCF from being set between the time it is read and the time

the output compare registers are updated, use this procedure:

7. Disable interrupts by setting the I bit in the condition code register.

8. Write to OCRH. Compares are now inhibited until OCRL is written.

9. Clear bit OCF by reading timer status register (TSR).

10. Enable the output compare function by writing to OCRL.

11. Enable interrupts by clearing the I bit in the condition code

OCRH

$0016

Bit 7

Bit 0

Write:

BIT15

BIT14

BIT13

BIT12

BIT11

BIT10

BIT9

BIT8

Read:

Unaffected by Reset

OCRL

$0017

Bit 7

Bit 0

Write:

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

Read:

Unaffected by Reset

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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