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ICS9LPRS477C データシート(PDF) 10 Page - Renesas Technology Corp |
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ICS9LPRS477C データシート(HTML) 10 Page - Renesas Technology Corp |
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10 / 25 page  IDT® Programmable System Clock Chip for ATI RD790-K8TM Based Systems 1393—01/28/14 9LPRS477C Programmable System Clock Chip for ATI RD790 - K8TM based Systems 10 SMBus Table: Latched Input Readback Output Enable Control Register Byte 0 Name Description Type 0 1 Default Bit 7 SEL_HTT66 readback Hypertransport Select R 100MHz Differential HTT clock 66 MHz 3.3V Single-ended HTT clock Latch Bit 6 SEL_SATA readback SATA Select R SRC6/SATA pair is SRC SS capable output SRC6/SATA pair is SATA non- spread output Latch Bit 5 REF0_OE Output Enable RW Hi-Z Enabled 1 Bit 4 REF1_OE Output Enable RW Hi-Z Enabled 1 Bit 3 REF2_OE Output Enable RW Hi-Z Enabled 1 Bit 2 48MHz_1_OE Output Enable RW Low Enabled 1 Bit 1 48MHz_0_OE Output Enable RW Low Enabled 1 Bit 0 SEL_CPU1 readback CPU1/SRC7 Select R CPU1 Differential output SRC7 Differential output Latch SMBus Table:Output Enable Control Register Byte 1 Name Control Function Type 0 1 Default Bit 7 SEL_DOC readback DOC Select R SRC5 Differential output DOC Latch Bit 6 SRC6/SATA_OE Enable Output Enable RW Low /Low Enabled 1 Bit 5 SRC5_OE Output Enable RW Low /Low Enabled 1 Bit 4 SRC4_OE Output Enable RW Low /Low Enabled 1 Bit 3 SRC3_OE Output Enable RW Low /Low Enabled 1 Bit 2 SRC2_OE Output Enable RW Low /Low Enabled 1 Bit 1 SRC1_OE Output Enable RW Low /Low Enabled 1 Bit 0 SRC0_OE Output Enable RW Low /Low Enabled 1 SMBus Table: Output Enable and 48MHz Strength Control Register Byte 2 Name Control Function Type 0 1 Default Bit 7 SB_SRC1_OE Output Enable RW Low /Low Enabled 1 Bit 6 SB_SRC0_OE Output Enable RW Low /Low Enabled 1 Bit 5 ATIG3_OE Output Enable RW Low /Low Enabled 1 Bit 4 ATIG2_OE Output Enable RW Low /Low Enabled 1 Bit 3 ATIG1_OE Output Enable RW Low /Low Enabled 1 Bit 2 ATIG0_OE Output Enable RW Low /Low Enabled 1 Bit 1 48MHz_1_Strength 48MHz_1 Drive Strength Sel. RW 1 Load 2 Load 1 Bit 0 48MHz_0_Strength 48MHz_0 Drive Strength Sel. RW 1 Load 2 Load 1 SMBus Table: CPU/HTT Frequency Control Register Byte 3 Name Control Function Type 0 1 Default Bit 7 CPU1_OE/SRC7_OE Output enable RW Low /Low Enable 1 Bit 6 CPU0_OE Output enable RW Low /Low Enable 1 Bit 5 CPU Spread Source CPU Spread Source RW Fix PLL SB_SRC PLL 1 Bit 4 CPU_FS4 CPU Frequency Select MSB RW 0 Bit 3 CPU_FS3 CPU Frequency Select RW 1 Bit 2 CPU_FS2 CPU Frequency Select RW 1 Bit 1 CPU_FS1 CPU Frequency Select RW 1 Bit 0 CPU_FS0 CPU Frequency Select LSB RW 1 SMBus Table: SRC Frequency Control Register Byte 4 Name Control Function Type 0 1 Default Bit 7 REF0_Strength REF0_Drive Strength Sel RW 1 Load 2 Load 1 Bit 6 REF1_Strength REF1_Drive Strength Sel RW 1 Load 2 Load 1 Bit 5 REF2_Strength REF2_Drive Strength Sel RW 1 Load 2 Load 1 Bit 4 0 Bit 3 SRC_FS3 SRC Frequency Select RW 1 Bit 2 SRC_FS2 SRC Frequency Select RW 1 Bit 1 SRC_FS1 SRC Frequency Select RW 1 Bit 0 SRC_FS0 SRC Frequency Select LSB RW 1 See CPU Frequency Select Table Default value corresponds to 200MHz. Note that Selected HTT frequency tracks the CPU frequency. Reserved See SRC Frequency Select Table |
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