IDT®

Programmable System Clock Chip for ATI RD790-K8TM Based Systems

1393—01/28/14

9LPRS477C

Programmable System Clock Chip for ATI RD790 - K8TM based Systems

22

Clock Jitter Specifications - Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

t

jphasePLL

PCIe Gen 1

86

ps (p-

p)

1,2

t

jphaseLo

PCIe Gen 2

10kHz < f < 1.5MHz

3

ps

(RMS)

1,4

t

jphaseHigh

PCIe Gen 2

1.5MHz < f < Nyquist (50MHz)

3.1

ps

(RMS)

1,4

*TA = 0 - 70°C; Supply Voltage VDD = 3.3V +/-5%, Rs = 0ohms, CL = 2pF

4

See http://www.pcisig.com for complete specs

SRC/SB_SRC/ATIG

Phase Jitter

1

Unless otherw ise noted, guaranteed by design and characterization, not 100% tested in production.

2

JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use

these numbers, as the in-system performance w ill be somew hat degraded. The receiver EMTS (chispet or CPU) w ill have the rece

3

Phase jitter requirement: The deisgnated Gen2 outputs w ill meet the reference clock jitter requiremernts from the PCI Express Gen2

Base Spec. The test is performed on a componnet test board under quiet condittions w ith all outputs on.