IDT®

Programmable System Clock Chip for ATI RD790-K8TM Based Systems

1393—01/28/14

9LPRS477C

Programmable System Clock Chip for ATI RD790 - K8TM based Systems

16

SMBUS Table: CPU PLL DOC 3 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 11)

Byte

34

Name

Control Function

Type

0

1

Default

Bit 7

N Div10

RW

X

Bit 6

N Div9

RW

X

Bit 5

N Div8

RW

X

Bit 4

N Div7

RW

X

Bit 3

N Div6

RW

X

Bit 2

N Div5

RW

X

Bit 1

N Div4

RW

X

Bit 0

N Div3

RW

X

SMBUS Table: ATIG PLL DOC 1 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 01)

Byte

35

Name

Control Function

Type

0

1

Default

Bit 7

N Div10

RW

X

Bit 6

N Div9

RW

X

Bit 5

N Div8

RW

X

Bit 4

N Div7

RW

X

Bit 3

N Div6

RW

X

Bit 2

N Div5

RW

X

Bit 1

N Div4

RW

X

Bit 0

N Div3

RW

X

SMBUS Table: ATIG PLL DOC 2 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 10)

Byte

36

Name

Control Function

Type

0

1

Default

Bit 7

N Div10

RW

X

Bit 6

N Div9

RW

X

Bit 5

N Div8

RW

X

Bit 4

N Div7

RW

X

Bit 3

N Div6

RW

X

Bit 2

N Div5

RW

X

Bit 1

N Div4

RW

X

Bit 0

N Div3

RW

X

SMBUS Table: ATIG PLL DOC 3 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 11)

Byte

37

Name

Control Function

Type

0

1

Default

Bit 7

N Div10

RW

X

Bit 6

N Div9

RW

X

Bit 5

N Div8

RW

X

Bit 4

N Div7

RW

X

Bit 3

N Div6

RW

X

Bit 2

N Div5

RW

X

Bit 1

N Div4

RW

X

Bit 0

N Div3

RW

X

SMBUS Table: SRC PLL DOC 1 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 01)

Byte

38

Name

Control Function

Type

0

1

Default

Bit 7

N Div10

RW

X

Bit 6

N Div9

RW

X

Bit 5

N Div8

RW

X

Bit 4

N Div7

RW

X

Bit 3

N Div6

RW

X

Bit 2

N Div5

RW

X

Bit 1

N Div4

RW

X

Bit 0

N Div3

RW

X

SMBUS Table: SRC PLL DOC 2 N programming Register (1 pin control : DOC = 1; 2 pin control : DOC [0:1] = 10)

Byte

39

Name

Control Function

Type

0

1

Default

Bit 7

N Div10

RW

X

Bit 6

N Div9

RW

X

Bit 5

N Div8

RW

X

Bit 4

N Div7

RW

X

Bit 3

N Div6

RW

X

Bit 2

N Div5

RW

X

Bit 1

N Div4

RW

X

Bit 0

N Div3

RW

X

N Divider Programming Byte20

bit(7:0) and Byte19 bit(7:6)

The decimal representation of M and N Divider in Byte 21 and 38

w ill configure the VCO frequency. Default at pow er up = Byte

4 Rom table. See M/N Caculation Tables for VCO frequency

formulas.

N Divider Programming Byte20

bit(7:0) and Byte19 bit(7:6)

The decimal representation of M and N Divider in Byte 21 and 39

w ill configure the VCO frequency. Default at pow er up = Byte

4 Rom table. See M/N Caculation Tables for VCO frequency

formulas.

The decimal representation of M and N Divider in Byte 16 and 34

w ill configure the VCO frequency. Default at pow er up = Byte

3 Rom table. See M/N Caculation Tables for VCO frequency

formulas.

The decimal representation of M and N Divider in Byte 26 and 35

w ill configure the VCO frequency. Default at pow er up = Byte

5 Rom table. See M/N Caculation Tables for VCO frequency

formulas.

N Divider Programming Byte20

bit(7:0) and Byte19 bit(7:6)

The decimal representation of M and N Divider in Byte 26 and 36

w ill configure the VCO frequency. Default at pow er up = Byte

5 Rom table. See M/N Caculation Tables for VCO frequency

formulas.

N Divider Programming Byte20

bit(7:0) and Byte19 bit(7:6)

The decimal representation of M and N Divider in Byte 26 and 37

w ill configure the VCO frequency. Default at pow er up = Byte

5 Rom table. See M/N Caculation Tables for VCO frequency

formulas.

N Divider Programming Byte20

bit(7:0) and Byte19 bit(7:6)

N Divider Programming Byte20

bit(7:0) and Byte19 bit(7:6)