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ICS9LPRS477D データシート(PDF) 14 Page - Renesas Technology Corp

部品番号 ICS9LPRS477D
部品情報  PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS
PDF  27 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS9LPRS477D データシート(HTML) 14 Page - Renesas Technology Corp

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9LPRS477D
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS
IDT®
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS
14
9LPRS477D
REV C 010715
SMBUS Table: ATIG Frequency Control Register
Byte
26
Name
Control Function
Type
0
1
Default
Bit 7
N Div2
N Divider Prog bit 2
RW
X
Bit 6
N Div1
N Divider Prog bit 1
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
SMBUS Table: ATIG Frequency Control Register
Byte
27
Name
Control Function
Type
0
1
Default
Bit 7
N Div10
RW
X
Bit 6
N Div9
RW
X
Bit 5
N Div8
RW
X
Bit 4
N Div7
RW
X
Bit 3
N Div6
RW
X
Bit 2
N Div5
RW
X
Bit 1
N Div4
RW
X
Bit 0
N Div3
RW
X
SMBUS Table: ATIG Output Divider C ontrol Register
Byte
28
Name
Control Function
Type
0
1
Default
Bit 7
ATIG NDiv0
LSB N Di vider Programming
RW
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
ATIGDiv3
RW
0000:/2 ; 0100:/4
1000:/8 ; 1100:/16
X
Bit 2
ATIGDiv2
RW
0001:/3 ; 0101:/6
1001:/12 ; 1101:/24
X
Bit 1
ATIGDiv1
RW
0010:/5 ; 0110:/10
1010:/20 ; 1110:/40
X
Bit 0
ATIGDiv0
RW
0011:/9 ; 0111:/18
1011:/36 ; 1111:/72
X
SMBUS Table: SB _SRC Frequency Control Register
Byte
29
Name
Control Function
Type
0
1
Default
Bit 7
N Div2
N Divider Prog bit 2
RW
X
Bit 6
N Div1
N Divider Prog bit 1
RW
X
Bit 5
M Div5
RW
X
Bit 4
M Div4
RW
X
Bit 3
M Div3
RW
X
Bit 2
M Div2
RW
X
Bit 1
M Div1
RW
X
Bit 0
M Div0
RW
X
SMBUS Table: SB _SRC Frequency Control Register
Byte
30
Name
Control Function
Type
0
1
Default
Bit 7
N Div10
RW
X
Bit 6
N Div9
RW
X
Bit 5
N Div8
RW
X
Bit 4
N Div7
RW
X
Bit 3
N Div6
RW
X
Bit 2
N Div5
RW
X
Bit 1
N Div4
RW
X
Bit 0
N Div3
RW
X
SMBUS Table: SB _SRC Output Divider Control Register
Byte
31
Name
Control Function
Type
0
1
Default
Bit 7
SB_SRC NDiv0
LSB N Di vider Programming
RW
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
SB_SRCDiv3
RW
0000:/2 ; 0100:/4
1000:/8 ; 1100:/16
X
Bit 2
SB_SRCDiv2
RW
0001:/3 ; 0101:/6
1001:/12 ; 1101:/24
X
Bit 1
SB_SRCDiv1
RW
0010:/5 ; 0110:/10
1010:/20 ; 1110:/40
X
Bit 0
SB_SRCDiv0
RW
0011:/9 ; 0111:/18
1011:/36 ; 1111:/72
X
The decimal representation of M and N Divider in Byte 26 and 27 will
configure the VCO frequency. Default at power up = Byte 5 Rom
table. See M/N Caculation Tables for VCO frequency formulas.
M Divider Programming
bit (5:0)
N Divider Programming Byte20
bit(7:0) and Byte19 bit(7:6)
The decimal representation of M and N Divider in Byte 26 and 27 will
configure the VCO frequency. Default at power up = Byte 5 Rom
table. See M/N Caculation Tables for VCO frequency formulas.
N Divider LSB (bit 0) for ATIG M/N programming.
Reserved
Reserved
Reserved
ATIG Divider Ratio Programming Bits
The decimal representation of M and N Divider in Byte 29 and 30 will
configure the VCO frequency. Default at power up = Byte 6 Rom
table. See M/N Caculation Tables for VCO frequency formulas.
M Divider Programming
bit (5:0)
N Divider Programming Byte20
bit(7:0) and Byte19 bit(7:6)
The decimal representation of M and N Divider in Byte 29 and 30 will
configure the VCO frequency. Default at power up = Byte 6 Rom
table. See M/N Caculation Tables for VCO frequency formulas.
N Divider LSB (bit 0) for SRC M/N programming.
Reserved
Reserved
Reserved
SB_SRC Divider Ratio Programming
Bits



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