9LPRS477D

PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS

IDT®

PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8TM BASED SYSTEMS

18

9LPRS477D

REV C 010715

AC Electrical Characteristics–Low-Power DIF Outputs: CPUKG and HTT

P ARAMETE R

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Cro ssing Point Variation

∆V

CROSS

Single-ended Measurement

140

mV

1,2,5

Frequency

f

Spread Specturm On

198.8

200

MHz

1,3

Long Term Accuracy

ppm

Spread Specturm Off

-300

+300

ppm

1,1 1

Rising Edge Slew Rate

S

RISE

Differential Measurement

0.5

10

V/ns

1,4

Falling Edge Slew Rate

S

FALL

Differential Measurement

0.5

10

V/ns

1,4

Slew Rate Variation

t

SLVAR

Single-ended Measurement

20

%

1

CPU, DIF HTT

Jitter - Cycle to Cycle

CPUJC2C

Differential Measurement

150

ps

1,6

Accumulated Jitter

tJACC

See Notes

1

ns

1,7

Peak to P eak Differential Voltage

VD(PK-PK)

Differential Measurement

400

2400

mV

1,8

Differential Voltage

V

D

Differential Measurement

200

1200

mV

1,9

Duty Cycle

D

CYC

Differential Measurement

45

55

%

1

Amplitude Variation

∆V

D

Change in VD DC cycle to cycle

-75

75

mV

1,1 0

CPU[1:0] Skew

CPU

SKEW1 0

Differential Measurement

100

ps

1

*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%, CL = 2pF with Rs = 0Ω (unless otherwise specified)

1Guaranteed by design and characterization, not 100% tested in production.

3Minimum Frequency is a result of 0.5% down spread spectrum

6 Max difference of t

CYC LE between a ny two adjacent cycles.

8 VD(PK-PK) is the overall magnitude of the differential signal.

11 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz

9 VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V VD. VD(max) is the

largest amplitude allowed.

10 The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of the signal.

2Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not important due to

the blocking cap.

4Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate spec when crossing

through this region.

5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling

edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.

7 Accumulated tjc.over a 10µs time period, measured with JIT2 TIE at 50ps interval.