IDTTM/ICSTM Programmable FTG for Differential P4

TM CPU, PCI-Express & SATA Clocks

ICS9FG107

REV F 08/21/07

ICS9FG107

Programmable FTG for Differential P4

TM CPU, PCI-Express & SATA Clocks

3

Pin Description

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1

XIN/CLKIN

IN

Crystal input or Reference Clock input

2

X2

OUT

Crystal output, Nominally 14.318MHz

3

VDD

PWR

Power supply, nominal 3.3V

4

GND

PWR

Ground pin.

5

FS2/REFOUT*

I/O

Frequency select latch input pin / Reference clock output

6

GND

PWR

Ground pin.

7

FS0/PCICLK_F*

I/O

Frequency select latch input pin / 3.3V PCI free running clock output.

8

PCICLK0

OUT

PCI clock output.

9

PCICLK1

OUT

PCI clock output.

10

VDD

PWR

Power supply, nominal 3.3V

11

OE_6**

IN

Active high input for enabling output 6.

0 = tri-state outputs, 1= enable outputs

12

DIF_6

OUT

0.7V differential true clock output

13

DIF_6#

OUT

0.7V differential complement clock output

14

VDD

PWR

Power supply, nominal 3.3V

15

GND

PWR

Ground pin.

16

OE_5**

IN

Active high input for enabling output 5.

0 = tri-state outputs, 1= enable outputs

17

DIF_5

OUT

0.7V differential true clock output

18

DIF_5#

OUT

0.7V differential complement clock output

19

VDD

PWR

Power supply, nominal 3.3V

20

DIF_4

OUT

0.7V differential true clock output

21

DIF_4#

OUT

0.7V differential complement clock output

22

OE_4*

IN

Active high input for enabling output 4.

0 = tri-state outputs, 1= enable outputs

23

SDATA

I/O

Data pin for SMBus circuitry, 3.3V tolerant.

24

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.