IDTTM/ICSTM Programmable FTG for Differential P4

TM CPU, PCI-Express & SATA Clocks

ICS9FG107

REV F 08/21/07

ICS9FG107

Programmable FTG for Differential P4

TM CPU, PCI-Express & SATA Clocks

10

Absolute Max

Electrical Characteristics - Input/Supply/Common Output Parameters

Symbol

Parameter

Min

Max

Units

VDD_A

3.3V Core Supply Voltage

VDD + 0.5V

V

VDD_In

3.3V Logic Input Supply Voltage

GND - 0.5

VDD + 0.5V

V

Ts

Storage Temperature

-65

150

°C

Tambient

Ambient Operating Temp

0

70

°C

Tcase

Case Temperature

115

°C

ESD prot

Input ESD protection

human body model

2000

V

TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input High Voltage

VIH

3.3 V +/-5%

2

VDD + 0.3

V

Input Low Voltage

VIL

3.3 V +/-5%

VSS - 0.3

0.8

V

Input High Current

IIH

VIN = VDD

-5

5

uA

IIL1

VIN = 0 V; Inputs with no pull-

up resistors

-5

uA

IIL2

VIN = 0 V; Inputs with pull-up

resistors

-200

uA

Full Active, CL = Full load;

f = 400 MHz

250

mA

Full Active, CL = Full load;

f = 100 MHz

200

mA

Input Frequency

3

Fi

VDD = 3.3 V

14

25

MHz

3

Pin Inductance

1

Lpin

7nH

1

CIN

Logic Inputs

1.5

5

pF

1

COUT

Output pin capacitance

6

pF

1

Clk Stabilization

1,2

TSTAB

From VDD Power-Up and after

input clock stabilization to 1st

clock

1.8

ms

1,2

Modulation Frequency

fMOD

Triangular Modulation

30

40

kHz

1

DIF output enable

tDIFOE

DIF output enable after

DIF_Stop# de-assertion

10

ns

1

Input Rise and Fall times

tR/tF

20% to 80% of VDD

5

ns

1

1Guaranteed by design and characterization, not 100% tested in production.

2See timing diagrams for timing requirements.

3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet

ppm frequency accuracy on PLL outputs.

Input/Output

Capacitance

1

Input Low Current

IDD3.3OP

Operating Supply Current