14

Integrated

Circuit

Systems, Inc.

ICS9FG1901

0962E—01/02/07

SMBusTable: Reserved Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

SMBus Table: 1:1 PLL Frequency Control Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

1:1 PLL N Div8

N Divider Prog bit 8

RW

X

Bit 6

1:1 PLL N Div9

N Divider Prog bit 9

RW

X

Bit 5

1:1 PLL M Div5

RW

X

Bit 4

1:1 PLL M Div4

RW

X

Bit 3

1:1 PLL M Div3

RW

X

Bit 2

1:1 PLL M Div2

RW

X

Bit 1

1:1 PLL M Div1

RW

X

Bit 0

1:1 PLL M Div0

RW

X

SMBus Table: 1:1 PLL Frequency Control Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

1:1 PLL N Div7

RW

X

Bit 6

1:1 PLL N Div6

RW

X

Bit 5

1:1 PLL N Div5

RW

X

Bit 4

1:1 PLL N Div4

RW

X

Bit 3

1:1 PLL N Div3

RW

X

Bit 2

1:1 PLL N Div2

RW

X

Bit 1

1:1 PLL N Div1

RW

X

Bit 0

1:1 PLL N Div0

RW

X

SMBusTable: 1:1 PLL Output Divider Register (Rev H and higher)

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

1:1 PLL OutDiv 3

PLL 2 Output Divider

RW

X

Bit 2

1:1 PLL OutDiv 2

PLL 2 Output Divider

RW

X

Bit 1

1:1 PLL OutDiv 1

PLL 2 Output Divider

RW

X

Bit 0

1:1 PLL OutDiv 0

PLL 2 Output Divider

RW

X

-

-

-

-

-

Byte 16

-

Byte 17

-

-

-

Byte 19

-

-

Byte 18

-

-

-

-

-

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

See Output Divider Table

N Divider Programming b(7:0)

RESERVED

RESERVED

RESERVED

M Divider Programming bits