2

Integrated

Circuit

Systems, Inc.

ICS9FG1901

0962E—01/02/07

Pin Description

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1

IREF

OUT

This pin establishes the reference current for the differential current-mode output

pairs. This pin requires a fixed precision resistor tied to ground in order to

establish the appropriate current. 475 ohms is the standard value.

2

GNDA

PWR

Ground pin for the PLL core.

3

VDDA/PD#

PWR

3.3V power for the PLL core that also functions as Power Down. Collapsing this

power supply places the device in Power Down mode.

4HIGH_BW#

IN

3.3V input for selecting PLL Band Width

0 = High, 1= Low

5FS_A_410

IN

3.3V tolerant low threshold input for CPU frequency selection. This pin requires

CK410 FSA. Refer to input electrical characteristics for Vil_FS and Vih_FS

threshold values.

6

DIF_0

OUT

0.7V differential true clock output

7

DIF_0#

OUT

0.7V differential complement clock output

8

DIF_1

OUT

0.7V differential true clock output

9

DIF_1#

OUT

0.7V differential complement clock output

10

GND

PWR

Ground pin.

11

VDD

PWR

Power supply, nominal 3.3V

12

DIF_2

OUT

0.7V differential true clock output

13

DIF_2#

OUT

0.7V differential complement clock output

14

DIF_3

OUT

0.7V differential true clock output

15

DIF_3#

OUT

0.7V differential complement clock output

16

DIF_4

OUT

0.7V differential true clock output

17

DIF_4#

OUT

0.7V differential complement clock output

18

OE_01234#

IN

Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.

1 = tri-state outputs, 0 = enable outputs

19

SMBCLK

IN

Clock pin of SMBUS circuitry, 5V tolerant

20

SMBDAT

I/O

Data pin of SMBUS circuitry, 5V tolerant

21

OE5#

IN

Active low input for enabling DIF pair 5.

1 = tri-state outputs, 0 = enable outputs

22

DIF_5

OUT

0.7V differential true clock output

23

DIF_5#

OUT

0.7V differential complement clock output

24

OE6#

IN

Active low input for enabling DIF pair 6.

1 = tri-state outputs, 0 = enable outputs

25

DIF_6

OUT

0.7V differential true clock output

26

DIF_6#

OUT

0.7V differential complement clock output

27

VDD

PWR

Power supply, nominal 3.3V

28

GND

PWR

Ground pin.

29

OE7#

IN

Active low input for enabling DIF pair 7.

1 = tri-state outputs, 0 = enable outputs

30

DIF_7

OUT

0.7V differential true clock output

31

DIF_7#

OUT

0.7V differential complement clock output

32

OE8#

IN

Active low input for enabling DIF pair 8.

1 = tri-state outputs, 0 = enable outputs

33

DIF_8

OUT

0.7V differential true clock output

34

DIF_8#

OUT

0.7V differential complement clock output

35

SMB_A0

IN

SMBus address bit 0 (LSB)

36

SMB_A1

IN

SMBus address bit 1