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November 16, 2007

IDT70P9268

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM

Industrial Temperature Range

Device Description

Designed primarily for use as a high-speed, low-power inter-connect in multi-processor wireless handsets, the IDT70P9268 or Mobile Multimedia

Interconnect (M2I) provides many advantages over embedded serial interfaces, asynchronous memories, and other legacy solutions to inter-

processor communication.

Performance

The M2I supports unparalleled data throughput rates of up to 900 Mbps per port. This is achieved through the implementation of a synchronous archi-

tecture which allows the device to support much shorter cycle times (20 ns compared to 55 ns for most low-power asynchronous memories). Addition-

ally, the adoption of a synchronous architecture allows the M2I to support on-chip counter functionality which helps to eliminate the inefficiencies

associated with asynchronous implementations of the address-data-multiplex (ADM) interface. Asynchronous ADM (address-data multiplex) inter-

faces require the assertion of an external address on one cycle followed by the associated data on the subsequent cycle. This results in an access

scheme that imparts a 50% inefficiency into a system already limited by slow cycle times. The M2I’s counter functionality allows a single external

address to be asserted on one cycle followed by data being burst into or out of the device on every subsequent cycle. This, when combined with the

dramatically improved cycle time, translates to roughly six times greater throughput per-port when compared with asynchronous ADM devices.

Power Consumption

In portable applications, power consumption is of vital concern. This is why the M2I includes several features targeted at reducing the power consump-

tion of the device itself and the system as a whole. First, the M2I was designed to consume 40% less operating current than low-power asynchronous

memories (15 mA compared to 25 mA). When combined with it’s superior performance and counter functionality, which allow it to complete media

transfers in fewer cycles, this enables the M2I to consume nearly 90% less energy than asynchronous memories during transfers of a given file size.

Second, the M2I features port-specific chip-enable and sleep mode pins which allow the two ports of the M2I to be powered down into standby mode

independently of one another. When combined with the M2I’s interrupt flag functionality, this allows the processor subsystems to communicate with

one another and to shut off whole portions of the handset which are not in use, dramatically reducing the power consumption of the system.

Flexibility

To help meet the ever changing requirements of wireless handsets, the M2I has been designed to provide a great deal of flexibility. The M2I has the

ability to support both ADM and traditional SRAM interfaces, allowing it to seamlessly interface with both current and legacy processors. Additionally,

the M2I helps to free up GPIO pins on the processors, allowing designers to include differentiating functionality that helps set their product apart from

the competition. By supporting the ADM interface, the M2I consumes nearly 50% fewer pins per-port than non-multiplexed solutions. The M2I also

frees up additional GPIO pins on the processors by including 8 dynamically programmable GPIO extender pins. These pins allow the processors to

offload the need to monitor or control simple, binary state devices (e.g. switches, LED drivers, etc.) to the M2I and allow the processors to use their

GPIO pins for more value added functions.