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November 16, 2007

IDT70P9268

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM

Industrial Temperature Range

Special Function I/O Operation

The PDR determines whether the SFX pins will operate as IRR or ODR. The PDR is programmed by writing to address x0000 with

SFEN = VIL and

I/O8 = H. Writing a “0” to I/OX will set SFX to be an IRR pin. Writing a “1” to I/OX will set SFX to be an ODR pin.

The status of the Special Function pins and the PDR can be read as a standard memory access to address x0000 from either port and the data is

output via the standard I/Os (Truth Table V). During Special Function reads I/O0 - I/O7 output the status of the Special Function pins with I/On corre-

sponding to SFn. I/O8 - I/O15 outputs the status of the Pin Direction Register with I/On = PDRn-8.

For SF pins set to ODR operation, the status of these pins is determined by using standard write accesses from either port to address x0000 with

SFEN = VIL and I/O8 = L. A written “1” will correspond to “on” for the connected binary state device and a written “0” will correspond to “off”.

Sleep Mode

The IDT70P9268 is equipped with an optional sleep or low-power mode on both ports. The sleep mode pin on both ports is asynchronous and active

high. During normal operation, the ZZ-pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will meet lowest possible power

conditions. The sleep mode timing diagram shows the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode.

For normal operation all inputs must meet setup and hold times prior to sleep and after recovering from sleep. Clocks must also meet cycle high and

low times during these periods. Three cycles prior to asserting ZZ (ZZX = VIH) and three cycles after de-asserting ZZ (ZZX = VIL), the device must be

disabled via the chip enable pins. If a write or a read operation occurs during these periods, the memory array may be corrupted. Validity of data out

from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep). When exiting sleep mode, the device must be in Read

mode (R/

WX = VIH) when chip enable is asserted, and the chip enable must be valid for one full cycle before a read will result in the output of valid

data.

During sleep mode the RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run

without impacting the RAMs sleep current (IZZ). All outputs will remain in high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM

will not be selected and will not perform any reads or writes.

I/O

Func tion

0 – 7

With

SFEN = L, I/O 8 = H , th e valu e w ritten to address 0 on I/O n w ill determ ine the

status of P D R n (1 = ou tput, 0 = in put). W ith

SFEN = L, I/O 8 = L, th e value w ritte n to

address 0 o n I/O n w ill be in put to th e corre spon din g O D R n lo cation (1 = on, 0 = off).

8

With

SFEN = L, w ritin g a “0” to a ddress 0 o n th is I/O ca uses the va lues of I/O 0 – I/O 7 to

be inpu t to th e ir c o rre spon d ing O D R lo cations. W ith

SFEN = L, w ritin g a “1” to a d dress

0 on th is I/O caus es th e values of I/O 0 – I/O 7 to b e in p u t to th e ir c o rre s p o n d in g P D R

lo cations, w h ic h in tu rn determ ine w h eth e r S F 0 – S F 7 are in dividu ally program m ed to

b e in p u ts (IR R ) o r o u tp u ts (O D R ).

9 – 1 5

With

SFEN = L, rea ds to ad dress 0 w ill output the sta tu s of the P D R , w h ere I/O n =

P DRn -8