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November 16, 2007

IDT70P9268

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM

Industrial Temperature Range

Functional Description

The 70P9268L provides a true synchronous multiplexed and non-multiplexed Dual-Port Static RAM interface. Registered inputs provide minimal set-

up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. Counter

enable and counter repeat inputs are provided to facilitate burst reads and writes to the memory.

Synchronous Interrupts

If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (

INTL) is

asserted when the right port writes to memory location 3FFE (HEX), where a write is defined as

CER = R/WR = VIL. The left port clears the interrupt

through access of address location 3FFE when

CEL = VIL, R/WL = VIH. Likewise, the right port interrupt flag (INTR) is asserted when the left port writes

to memory location 3FFF (HEX) and to clear the interrupt flag (

INTR), the right port must read the memory location 3FFF. The message (16 bits) at

3FFE or 3FFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address, locations 3FFE and 3FFF are not

used as mail boxes, but as part of the random access memory.

Truth Table IV - Interrupt Flag

Advanced Input Read and Output Drive Registers

The IDT70P9268L is equipped with 8 Special Function (SFX) pins that can be programmed to function as either Input Read Register (IRR) or Output

Drive Register (ODR) pins. IRR pins allow the user to capture the status of external binary state devices and report that status to a processor, ASIC,

FPGA, etc. via a standard read access from either port. ODR pins allow the user to monitor and control the state of external binary state devices via

standard reads and writes from either port. The functionality of the SF pins are determined by the status of the Pin Direction Register (PDR). Refer to

Truth Table V for information on programming the PDR and operating the special function pins.

Truth Table V - Input Read and Output Drive Registers

NOTES:

1. If I/On = H, SFn is programmed as an output and I/On will be used to read and write to this ODR location during subsequent transactions when I/O8 = L. If I/On= L, SFn is programmed

as an input and I/On will be used to read this IRR location during subsequent reads where I/O8 = L.

2. For n = 0-7. If PDRn = 0, I/On = IRRn (the registered value of SFn). If PDRn = 1, I/On = ODRn (the value last written to ODRn).

3. For n = 8-15, I/On = PDRn-8.

4. For I/O0 - I/O7, the value written to I/On will be input to each ODRn location (where PDRn = 1) with a “1” corresponding to “on” and a “0” corresponding to “off”.

Left Port

Right Port

CLKL

R/

W

L

CE

L

ADDL

INT

L

CLKR

R/

W

R

CE

R

ADDR

INT

R

Function

L

L

3FFF

X

X

X

X

L

Set Right INTR Flag

X

X

X

X

H

L

3FFF

H

Reset Right INTR Flag

X

X

X

L

L

L

3FFE

X

Set Left INTL Flag

H

L

3FFE

H

X

X

X

X

Reset Left INTL Flag

SFEN

ADDR

R/

W

I/O 0 – I/O 7

I/O 8

I/O 9 – I/O 15

Function

L

0

L

N ote 1

H

X

P rogram P in D irection R egister

L

0

H

N ote 2

N ote 3

Note 3

R eading the status of S F n and P DR n

L

0

L

N ote 4

L

X

W rite to O utput D rive R egister