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ICS1893CFILF データシート(PDF) 113 Page - Renesas Technology Corp

部品番号 ICS1893CFILF
部品情報  3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
PDF  127 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS1893CFILF データシート(HTML) 113 Page - Renesas Technology Corp

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Chapter 9 DC and AC Operating Conditions
ICS1893CF, Rev. K, 05/13/10
May, 2010
113
ICS1893CF Data Sheet Rev. J - Release
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
9.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
Table 9-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during
half-duplex transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
Figure 9-12 shows the timing diagram for the time periods.
Figure 9-12. 100M MII Carrier Assertion/De-Assertion Timing Diagram
(Half-Duplex Transmission Only)
Table 9-18. 100M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only)
Time
Period
Parameter
Condi-
tions
Min.
Typ.
Max.
Units
t1
TXEN Sampled Asserted to CRS Assert
0
3
4
Bit times
t2
TXEN De-Asserted to CRS De-Asserted
0
3
4
Bit times
t2
t1
TXEN
TXCLK
CRS



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