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PSD4235G2V-10UI データシート(PDF) 73 Page - STMicroelectronics |
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PSD4235G2V-10UI データシート(HTML) 73 Page - STMicroelectronics |
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73 / 100 page  73/100 PSD4256G6V This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Input Control Signals The PSD provides the option to turn off the ad- dress input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/ AS, PD0) and WRITE-Enable High-byte (WRH/ DBE, PD3)) to the PLD to save AC power con- sumption. These signals are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting bits 0, 2, 3, 4, 5 and 6 to a 1 in PMMR2. Table 50. ADP Counter Operation APD Enable Bit ALE PD Polarity ALE Level APD Counter 0 X X Not Counting 1 X Pulsing Not Counting 1 1 1 Counting (Generates PDN after 15 Clocks) 1 0 0 Counting (Generates PDN after 15 Clocks) |
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