ST7789V2 datasheet(44/319 Pages) SITRONIX

44 / 319 page

ST7789V2

Version 1.0

Page 44 of 319

2016/11

Sitronix Confidential

The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or

disclosed in whole or in part without prior written permission of Sitronix.

7.4.3

Serial Interface Characteristics (4-line serial):

Figure 5 4-line serial Interface Timing Characteristics

VDDI=1.65 to 3.3V, VDD=2.4 to 3.3V, AGND=DGND=0V, Ta=25

℃

Signal

Symbol

Parameter

MIN

MAX

Unit

Description

CSX

TCSS

Chip select setup time (write)

TCSH

Chip select hold time (write)

TCSS

Chip select setup time (read)

TSCC

Chip select hold time (read)

TCHW

Chip select “H” pulse width

SCL

TSCYCW

Serial clock cycle (Write)

-write command & data

ram

TSHW

SCL “H” pulse width (Write)

TSLW

SCL “L” pulse width (Write)

TSCYCR

Serial clock cycle (Read)

150

-read command & data

ram

TSHR

SCL “H” pulse width (Read)

TSLR

SCL “L” pulse width (Read)

D/CX

TDCS

D/CX setup time

TDCH

D/CX hold time

SDA

(DIN)

TSDS

Data setup time

TSDH

Data hold time

DOUT

TACC

Access time

For maximum CL=30pF

For minimum CL=8pF

TOH

Output disable time

Table 6 4-line serial Interface Characteristics

Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as

ST7789V2 データシート(PDF) 44 Page - Sitronix Technology Co., Ltd.

ST7789V2 データシート(HTML) 44 Page - Sitronix Technology Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード