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CS53L21 データシート(PDF) 51 Page - Cirrus Logic |
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CS53L21 データシート(HTML) 51 Page - Cirrus Logic |
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51 / 66 page ![]() DS700PP1 51 CS53L21 Function: The level of ADCX can be adjusted in 1.0 dB increments as dictated by the ADCx Soft and Zero Cross bits (SOFTx & ZCROSSx) from 0 to -96 dB. Levels are decoded in two’s complement, as shown in the table above. Note: When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should not be adjusted manually. 6.11 ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh) Note: The SPE_ENABLE bit in reg09h must be set to 1 to enable function control in this register. ADCX Mixer Channel Mute (MUTE_ADCMIXX) Default: 1 0 - Disabled 1 - Enabled Function: The ADC channel X input to the output mixer will mute when enabled. The muting function is affected by the SPEX Soft and Zero Cross bits (SPEX_SZC[1:0]). ADCX Mixer Volume Control (ADCMIXX_VOL[6:0]) Default = 000 0000 Function: The level of the ADCX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the SPEX Soft and Zero Cross bits (SPE_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as shown in the table above. 6.12 Channel Mixer (Address 18h) Note: The SPE_ENABLE bits in reg09h must be set to 1 to enable function control in this register. Channel Mixer (ADCx[1:0]) Default: 00 7 6 543 21 0 MUTE_ADCMIXx ADCMIXx_VOL6 ADCMIXx_VOL5 ADCMIXx_VOL4 ADCMIXx_VOL3 ADCMIXx_VOL2 ADCMIXx_VOL1 ADCMIXx_VOL0 Binary Code Volume Setting 001 1000 +12.0 dB ··· ··· 000 0000 0 dB 111 1111 -0.5 dB 111 1110 -1.0 dB ··· ··· 001 1001 -51.5 dB 7 6 5 432 10 Reserved Reserved Reserved Reserved ADCA1 ADCA0 ADCB1 ADCB0 ADCA[1:0] SDOUT ADCB[1:0] SDOUT 00 L 00 R |
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