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CS53L21 データシート(PDF) 53 Page - Cirrus Logic

部品番号 CS53L21
部品情報  Low Power, Stereo Analog to Digital Converter
PDF  66 Pages
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メーカー  CIRRUS [Cirrus Logic]
ホームページ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS53L21 データシート(HTML) 53 Page - Cirrus Logic

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DS700PP1
53
CS53L21
Function:
Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting
in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting.
The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and the SOFTx
& ZCROSS bit settings unless the disable bit for each function is enabled.
6.15 ALC Threshold (Address 1Eh)
Maximum Threshold (MAX[2:0])
Default: 000
Function:
Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack
rate.
Minimum Threshold (MIN[2:0])
Default: 000
Function:
Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at a rate set
in the release rate register until levels again reach this minimum threshold. The ALC uses this minimum as
a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the
minimum setting. This provides a more natural sound as the ALC attacks and releases.
7
6
5
432
10
MAX2
MAX1
MAX0
MIN2
MIN1
MIN0
Reserved
Reserved
MAX[2:0] Threshold
Setting
(dB)
000
0
001
-3
010
-6
011
-9
100
-12
101
-18
110
-24
111
-30
MIN[2:0]
Threshold
Setting
(dB)
000
0
001
-3
010
-6
011
-9
100
-12
101
-18
110
-24
111
-30



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