Nexperia

74VHC595; 74VHCT595

8-bit serial-in/serial-out or parallel-out shift register with output latches

STAGE 0

STAGES 1 TO 6

STAGE 7

FF0

D

CP

Q

R

LATCH

D

CP

Q

FF7

D

CP

Q

R

LATCH

D

CP

Q

mna555

D

Q

Q1 Q2 Q3 Q4 Q5 Q6

Q7

Q7S

Q0

DS

STCP

SHCP

OE

MR

Fig. 4. Logic diagram

6. Pinning information

6.1. Pinning

74VHC595

74VHCT595

Q1

VCC

Q2

Q0

Q3

DS

Q4

OE

Q5

STCP

Q6

SHCP

Q7

MR

GND

Q7S

001aak048

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 5. Pin configuration SOT109-1 (SO16) and

SOT403-1 (TSSOP16)

001aak049

74VHC595

74VHCT595

Q7

MR

Q6

SHCP

Q5

STCP

Q4

OE

Q3

DS

Q2

Q0

Transparent top view

7

10

6

11

5

12

4

13

3

14

2

15

terminal 1

index area

GND(1)

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND

Fig. 6. Pin configuration SOT763-1 (DHVQFN16)

74VHC_VHCT595

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© Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 3 — 25 June 2020

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