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ST72340 データシート(PDF) 48 Page - STMicroelectronics |
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ST72340 データシート(HTML) 48 Page - STMicroelectronics |
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48 / 191 page ![]() ST72340, ST72344, ST72345 48/191 POWER SAVING MODES (Cont’d) Figure 30. ACTIVE-HALT Timing Overview Figure 31. ACTIVE-HALT Mode Flow-chart Notes: 1. This delay occurs only if the MCU exits ACTIVE-HALT mode by means of a RESET. 2. Peripheral clocked with an external clock source can still be active. 3. Only the RTC interrupt and some specific inter- rupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to Table 8, “Interrupt Mapping,” on page 40 for more details. 4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits in the CC register are set to the current software priority level of the interrupt routine and restored when the CC register is popped. HALT RUN RUN 256 OR 4096 CYCLE DELAY (AFTER RESET) RESET OR INTERRUPT HALT INSTRUCTION FETCH VECTOR ACTIVE (Active Halt enabled) HALT INSTRUCTION RESET INTERRUPT 3) Y N N Y CPU OSCILLATOR PERIPHERALS 2) I[1:0] BITS ON OFF 10 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON OFF XX 4) ON CPU OSCILLATOR PERIPHERALS I[1:0] BITS ON ON XX 4) ON 256 OR 4096 CPU CLOCK CYCLE DELAY (MCCSR.OIE=1) (AWUCSR.AWUEN=0) |
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