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UPD6708 データシート(PDF) 21 Page - Renesas Technology Corp

部品番号 UPD6708
部品情報  MOS INTEGRATED CIRCUIT
PDF  74 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD6708 データシート(HTML) 21 Page - Renesas Technology Corp

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µPD6708
2.5
Bit Format
The IEBus communication frame bit format (concept) is shown in Figure 2-4.
Figure 2-4. IEBus Bit Format (Concept)
Logic “1”: Potential difference between bus lines (BUS+ pin and BUS– pin) is 20 mV or lower (low level).
Logic “0”: Potential difference between bus lines (BUS+ pin and BUS– pin) is 120 mV or higher (high level).
Preparation period:
The first or subsequent low-level (logic “1”) period
Synchronous period: The next high-level (logic “0”) period
Data period:
The period that expresses the bit value (logic “1”: low level; logic “0”: high level)
The synchronous period and data period have approximately the same length.
The IEBus uses bit-by-bit synchronization. The specifications for the total bit time and the periods allocated to the bits
depend on the type of transfer bit, and on whether the unit is the master unit or the slave unit.
5
Preparation Period Synchronous Period
Data Period
Logic "1"
Logic "0"
Preparation Period Synchronous Period
Data Period



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