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T89C5115-RATIM データシート(PDF) 94 Page - ATMEL Corporation |
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T89C5115-RATIM データシート(HTML) 94 Page - ATMEL Corporation |
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94 / 113 page ![]() 94 AT89C5115 4128F–8051–05/06 Table 69. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 Reset Value = XXXX X000b bit addressable 76 54 32 1 0 - - - - - POVRL PADCL - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2POVRL Timer Overrun Interrupt Priority Level Less Significant bit Refer to PI2CH for priority level. 1 PADCL ADC Interrupt Priority Level Less Significant bit Refer to PSPIH for priority level. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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