LTM4650 datasheet(21/36 Pages) AD

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LTM4650-2

Rev. 0

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Figure 11. Graphical Representation of JESD51-12 Thermal Coefficients

46502 F11

µModule DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

2. θJCbottom, the thermal resistance from the junction to

the bottom of the product case, is the junction-to-board

thermal resistance with all of the component power

dissipation flowing through the bottom of the package.

In the typical µModule, the bulk of the heat flows out

the bottom of the package, but there is always heat

flow out into the ambient environment. As a result, this

thermal resistance value may be useful for comparing

packages, but the test conditions don’t generally match

the user’s application.

3. θJCtop, the thermal resistance from the junction to the

top of the product case, is determined with nearly all

of the component power dissipation flowing through

the top of the package. As the electrical connections of

the typical µModule are on the bottom of the package,

it is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θJCbottom, this value may be useful

for comparing packages, but the test conditions don’t

generally match the user’s application.

4. θJB, the thermal resistance from the junction to the

printed circuit board, is the junction-to-board thermal

resistance where almost all of the heat flows through

the bottom of the µModule and into the board, and is

really the sum of the θJCbottom and the thermal resis-

tance of the bottom of the part through the solder

joints and through a portion of the board. The board

APPLICATIONS INFORMATION

temperature is measured at a specified distance from

the package using a two-sided, two-layered board. This

board is described in JESD 51-9.

A graphical representation of the aforementioned thermal

resistances is shown in Figure 11; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD 51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a µModule. For example, in nor-

mal board-mounted applications, never does 100% of the

device’s total power loss (heat) thermally conducts exclu-

sively through the top or exclusively through the bottom

of the µModule—as the standard defines for θJCtop and

θJCbottom, respectively. In practice, power loss is ther-

mally dissipated in both directions away from the pack-

age—granted, in the absence of a heat sink and airflow,

a majority of the heat flow is into the board.

Within a SIP (system-in-package) module, be aware that

there are multiple power devices and components dis-

sipating power, with the consequence that the thermal

resistances relative to different junctions of components

or die are not exactly linear with respect to total pack-

age power loss. To reconcile this complication without

sacrificing modeling simplicity—but also, not ignoring

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