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PCF8531 データシート(PDF) 13 Page - NXP Semiconductors

部品番号 PCF8531
部品情報  34 x 128 pixel matrix driver
PDF  44 Pages
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メーカー  PHILIPS [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCF8531 データシート(HTML) 13 Page - NXP Semiconductors

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2000 Feb 11
13
Philips Semiconductors
Product specification
34
× 128 pixel matrix driver
PCF8531
8.18.2
FUNCTION SET
8.18.2.1
PD
When PD = 1, the Power-down mode of the LCD driver is
active:
• All LCD outputs at VSS (display off)
• Power-on reset detection active, oscillator off
• VLCD can be disconnected
• I2C-bus is operational, commands can be executed
• RAM contents not cleared; RAM data can be written
• Register settings remain unchanged.
8.18.2.2
V
When V = 0 the horizontal addressing is selected.
The data is written into the DDRAM as shown in Fig.7.
When V = 1 the vertical addressing is selected. The data
is written into the DDRAM as shown in Fig.6. Icon data is
written independently of V when Y address is 5.
8.18.3
SET Y ADDRESS
Bits Y2,Y1 and Y0 define the Y address vector of the
display RAM.
Table 1
Y address
8.18.4
SET X ADDRESS
The X address points to the columns. The range of X is
0 to 127 (7FH).
8.18.5
SET MULTIPLEX RATE
M[1:0] selects the multiplex rate (see Table 8).
8.18.6
DISPLAY CONTROL (D, E AND IM)
Bits D and E select the display mode (see Table 6). Bit IM
sets the display to icon mode.
8.18.7
SET BIAS SYSTEM
Different multiplex rates require different bias settings.
These are programmed by BS[2:0], which sets the binary
number n. The optimum value for n is given by
Supported values of n are given in Table 2. Table 3 shows
the intermediate bias voltages.
Y2
Y1
Y0
BANK
0000
0011
0102
0113
1004
1
0
1
5 (icons)
n
Mux rate
3
=
Table 2
Programming the required bias system
BS[2]
BS[1]
BS[0]
n
BIAS SYSTEM
COMMENT
0007
1
11
0016
1
10
0105
1
9
0114
1
8
1003
1
7
recommended for 1 : 34
1012
1
6
recommended for 1 : 26
1101
1
5
recommended for 1 : 17
1110
1
4
recommended for icon mode



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