PCF8531USLASH2 datasheet(20/44 Pages) PHILIPS

20 / 44 page

2000 Feb 11

Philips Semiconductors

Product speciﬁcation

× 128 pixel matrix driver

PCF8531

9.2

I2C-bus protocol

This driver does not support ‘read’. The PCF8531 is a

slave receiver. Therefore, it only responds when R/W=0

in the slave address byte.

Before any data is transmitted on the I2C-bus, the device

that should respond is addressed first. Two 7-bit slave

addresses (0111100 and 0111101) are reserved for the

PCF8531. The least significant bit of the slave address is

set by connecting the input SA0 to either logic 0 (VSS) or

logic 1 (VDD).

The I2C-bus protocol is illustrated in Fig.14.

The sequence is initiated with a START condition (S) from

the I2C-bus master, and is followed by the slave address.

All slaves with the corresponding address acknowledge in

parallel, all others ignore the I2C-bus transfer. After

acknowledgement, one or more command words follow,

which define the status of the addressed slaves.

A command word consists of a control byte, which defines

Co and RS, plus a data byte (see Fig.14 and Table 1).

The last control byte is tagged with a cleared most

significant bit, the continuation bit Co. The control and data

bytes are also acknowledged by all addressed slaves on

the bus.

After the last control byte, depending on the RS bit setting,

either a series of display data bytes or command data

bytes may follow. If the RS bit was set to logic 1, these

display bytes are stored in the display RAM at the address

specified by the data pointer.

The data pointer is automatically updated and the data is

directed to the intended PCF8531 device. If the RS bit of

the last control byte was set to logic 0, these command

bytes will be decoded and the setting of the device will be

changed according to the received commands.

The acknowledgement after each byte is made only by the

addressed PCF8531. At the end of the transmission, the

I2C-bus master issues a STOP condition (P).

9.3

Command decoder

• Pairs of bytes; information in the second byte, the first

byte determines whether information is display or

instruction data

• Stream of information bytes after Co = 0; display or

instruction data, depending on last RS (Register

Selection).

The command decoder identifies command words that

arrive on the I2C-bus. The most significant bit of a control

byte is the continuation bit Co. If this bit is logic 1, it

indicates that only one data byte (either command or RAM

data) will follow. If this bit is logic 0, it indicates that a series

of data bytes (either command or RAM data) may follow.

The DB6 bit of a control byte is the RAM data/command

bit RS. When this bit is at logic 1, it indicates that another

RAM data byte will be transferred next. If the bit is at

logic 0, it indicates that another command byte will be

transferred next.

handbook, full pagewidth

MGS474

011110

SA0

slave address

R/W

XXXXXX

control byte

Fig.14 Slave address and control byte.

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