MFS5600AMBAFES datasheet(47/118 Pages) NXP

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NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

WDW_DC [2:0]

CLOSED window

OPEN window

Others

50 %

Table 39. Watchdog window duty cycle configuration...continued

17.3.1 Simple watchdog

The simple watchdog uses a seed value that must be used to ‘pet’ the watchdog. The MCU can send its

own seed in WD_SEED register or use the default seed value 0x5AB2. This seed must be written in the

WD_ANSWER register during the OPEN watchdog window.

When the result is right, the watchdog window is restarted. When the result is wrong, a watchdog error counter

is incremented and the watchdog window is restarted. See Section 17.3.3 for watchdog error counter.

In case the watchdog answer from MCU is wrong, the “WD_BAD_DATA” bit is set to 1. In case the watchdog

answer (temporal domain) is wrong (timeout or refresh during closed window), the “WD_BAD_TIMING” bit is set

to 1.

In the simple watchdog configuration, it is not possible to write 0xFFFF and 0x0000 to the WD_SEED register. A

communication error (I2C_REQ_ERR = 1) is reported if writes of 0x0000 and 0xFFFF are attempted.

17.3.2 Challenger watchdog

The challenger watchdog is based on a question/answer process with the MCU. A 16-bit pseudo-random word

is generated by implementing a Linear Feedback Shift Register (LFSR) in the FS5600. The MCU can send the

seed of the LFSR or use the LFSR generated by the FS600 and will perform a pre-defined calculation. The

result should be sent through I2C during the OPEN watchdog window and is verified by the FS5600. When the

result is right, the watchdog window is restarted and a new LFSR is generated. When the result is wrong, the

WD error counter is incremented, the watchdog window is restarted and the LFSR value is not changed.

In case the watchdog answer from MCU is wrong, the “WD_BAD_DATA” bit is set to 1. In case the watchdog

answer (temporal domain) is wrong (timeout or refresh during closed window), the “WD_BAD_TIMING” bit is set

to 1.

During the initialization phase (INIT_RUN), the MCU can send the seed for the LFSR by writing to the

WD_SEED register, or use the default LFSR value generated by the FS5600 (0x5AB2). It is not possible to write

0x0000 to the WD_SEED register when in the challenger mode. The I2C_REQ_ERR bit is set when writing a

0x0000 is attempted.

Using the seed value, the MCU should perform a simple calculation based on the formula below, and send the

results in the WD_ANSWER register in the OPEN window for a valid watchdog refresh.

aaa-031017

WD_SEED[23:8]

WD_ANSWER[23:8]

NOT

Figure 13. Challenger watchdog formula

17.3.3 Watchdog error counter and error impact

The watchdog error counter is available for the Challenger and Simple watchdog schemes. The watchdog error

counter is used to count the number of bad watchdog refreshes (data and temporal errors).

Each time a watchdog failure occurs, the device increments this counter by 2. The watchdog error counter

decrements by 1 each time the watchdog is correctly refreshed. This principle ensures that a cyclic ’OK/NOK’

behavior converges to a failure detection.

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 29 April 2024

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