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MPC855T データシート(PDF) 39 Page - Freescale Semiconductor, Inc |
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MPC855T データシート(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 80 page  MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 39 Bus Signal Timing Table 12 shows the reset timing for the MPC860. Figure 31 shows the reset timing for the data bus configuration. Table 12. Reset Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit Min Max Min Max Min Max Min Max R69 CLKOUT to HRESET high impedance — 20.00 — 20.00 — 20.00 — 20.00 ns R70 CLKOUT to SRESET high impedance — 20.00 — 20.00 — 20.00 — 20.00 ns R71 RSTCONF pulse width 515.1 5 — 425.0 0 340.0 0 — 257.5 8 — ns R72 — — — — — — — — — R73 Configuration data to HRESET rising edge setup time 504.5 5 — 425.0 0 — 350.0 0 — 277.2 7 — ns R74 Configuration data to RSTCONF rising edge setup time 350.0 0 — 350.0 0 — 350.0 0 — 350.0 0 — ns R75 Configuration data hold time after RSTCONF negation 0.00 — 0.00 — 0.00 — 0.00 — ns R76 Configuration data hold time after HRESET negation 0.00 — 0.00 — 0.00 — 0.00 — ns R77 HRESET and RSTCONF asserted to data out drive — 25.00 25.00 — 25.00 — 25.00 ns R78 RSTCONF negated to data out high impedance — 25.00 — 25.00 — 25.00 — 25.00 ns R79 CLKOUT of last rising edge before chip three-state HRESET to data out high impedance — 25.00 — 25.00 — 25.00 — 25.00 ns R80 DSDI, DSCK setup 90.91 — 75.00 — 60.00 — 45.45 — ns R81 DSDI, DSCK hold time 0.00 — 0.00 — 0.00 — 0.00 — ns R82 SRESET negated to CLKOUT rising edge for DSDI and DSCK sample 242.4 2 — 200.0 0 — 160.0 0 — 121.2 1 — ns |
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