MPC855T datasheet(11/80 Pages) FREESCALE

11 / 80 page

MPC860 Family Hardware Specifications, Rev. 7

Freescale Semiconductor

Layout Practices

7.4 Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple two-resistor

model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the

package can be used in the thermal simulation.

7.5 Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the thermal

characterization parameter (

ΨJT) can be used to determine the junction temperature with a measurement of the

temperature at the top center of the package case using the following equation:

TJ = TT + (ΨJT × PD)

where:

JT = thermal characterization parameter

TT = thermocouple temperature on top of package

PD = power dissipation in package

The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40 gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the

thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and

over 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to

avoid measurement errors caused by cooling effects of the thermocouple wire.

7.6 References

Semiconductor Equipment and Materials International

(415) 964-5111

805 East Middlefield Rd.

Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) Specifications

800-854-7179 or

(Available from Global Engineering Documents)

303-397-7956

JEDEC Specifications

http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive

Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.

2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its

Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.

Layout Practices

Each VDD pin on the MPC860 should be provided with a low-impedance path to the board’s supply. Each GND pin

should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups of

logic on the chip. The VDD power supply should be bypassed to ground using at least four 0.1 µF-bypass capacitors

located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces

connecting to chip VDD and GND should be kept to less than half an inch per capacitor lead. A four-layer board

employing two inner layers as VCC and GND planes is recommended.

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