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MPC855T データシート(PDF) 59 Page - Freescale Semiconductor, Inc

部品番号 MPC855T
部品情報  Hardware Specifications
PDF  80 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC855T データシート(HTML) 59 Page - Freescale Semiconductor, Inc

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MPC860 Family Hardware Specifications, Rev. 7
Freescale Semiconductor
59
CPM Electrical Characteristics
Figure 58. Ethernet Collision Timing Diagram
Figure 59. Ethernet Receive Timing Diagram
134
TENA inactive delay (from TCLK1 rising edge)
10
50
ns
135
RSTRT active delay (from TCLK1 falling edge)
10
50
ns
136
RSTRT inactive delay (from TCLK1 falling edge)
10
50
ns
137
REJECT width low
1
—
CLK
138
CLKO1 low to SDACK asserted 2
—
20
ns
139
CLKO1 low to SDACK negated 2
—
20
ns
1
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 22. Ethernet Timing (continued)
Num
Characteristic
All Frequencies
Unit
Min
Max
CLSN(CTS1)
120
(Input)
RCLK1
121
RxD1
(Input)
121
RENA(CD1)
(Input)
125
124
123
127
126
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