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M65KA512AB データシート(PDF) 29 Page - STMicroelectronics

部品番号 M65KA512AB
部品情報  512Mbit (4 Banks x 8M x 16), 133 MHz Clock Rate, Bare Die, 1.8 V Supply, Low Power SDRAM
PDF  55 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M65KA512AB データシート(HTML) 29 Page - STMicroelectronics

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M65KA512AB
DC and ac parameters
29/55
Table 13.
AC characteristics 2
Symbol
Alt.
Parameter
M65KA512ABM65KA51
2AB
Unit
Min.
Max.
tDPL
Delay Time, Write Command to Data Input
2
-
(1)
tDAL
Data Input Valid to Precharge
Command
CAS Latency = 2
2*tCK + 22.5
-ns
CAS Latency = 3
-
ns
tMRD
tRSC
Mode Register Set Cycle Time
2
-
(1)
tRC
(2)
RAS Cycle Time (normal operation)
90
-
ns
tRC
RAS Cycle Time (refresh operation)
112.5
-
ns
tRC2
RAS Cycle Time (Self Refresh Exit to Refresh or
Bank/Row Activate Command)
120
-
ns
tRCD
Delay Time, RAS Active to CAS Active
27.5
-
ns
tRAS
RAS Active Time
60
120000
ns
tRP
RAS Precharge Time
22.5
-
ns
tRRD
Delay Time, RAS Active to RAS Bank Active
2
-
(1)
tREF
Refresh Time
-
64
ms
tT
Input Transition Time between VIL and VIH
0.5
30
ns
1.
The unit is the system Clock cycle time.
2.
A new command can be issued tRC after the Self Refresh mode is exited.



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